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Searched refs:SZ_4K (Results 1 – 25 of 34) sorted by relevance

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/rockchip-linux_mpp/utils/
H A Dmpi_dec_utils.h24 #define MPI_DEC_STREAM_SIZE (SZ_4K)
H A Dmpi_dec_utils.c37 #define DEFAULT_PACKET_SIZE SZ_4K
127 slot = mpp_malloc_size(FileBufSlot, MPP_ALIGN(sizeof(FileBufSlot) + data_size, SZ_4K)); in read_ivf_file()
231 buf_size = MPP_MAX(buf_size, SZ_4K); in check_file_type()
232 buf_size = MPP_ALIGN(buf_size, SZ_4K); in check_file_type()
/rockchip-linux_mpp/mpp/base/
H A Dmpp_dec_hdr_meta.c60 off = MPP_ALIGN(off, SZ_4K); in fill_hdr_meta_to_frame()
H A Dmpp_frame.c301 MPP_ALIGN(p->height, 16) / 16, SZ_4K); in mpp_frame_get_fbc_offset()
/rockchip-linux_mpp/mpp/hal/rkdec/h264d/
H A Dhal_h264d_vdpu34x.c46 #define VDPU34X_CABAC_TAB_ALIGNED_SIZE (MPP_ALIGN(VDPU34X_CABAC_TAB_SIZE, SZ_4K))
48 #define VDPU34X_SPSPPS_ALIGNED_SIZE (MPP_ALIGN(VDPU34X_SPSPPS_SIZE, SZ_4K))
49 #define VDPU34X_RPS_ALIGNED_SIZE (MPP_ALIGN(VDPU34X_RPS_SIZE, SZ_4K))
50 #define VDPU34X_SCALING_LIST_ALIGNED_SIZE (MPP_ALIGN(VDPU34X_SCALING_LIST_SIZE, SZ_4K))
559 RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (ver_virstride + 16) / 16, SZ_4K); in set_registers()
H A Dhal_h264d_vdpu382.c48 #define VDPU382_CABAC_TAB_ALIGNED_SIZE (MPP_ALIGN(VDPU382_CABAC_TAB_SIZE, SZ_4K))
50 #define VDPU382_SPSPPS_ALIGNED_SIZE (MPP_ALIGN(VDPU382_SPSPPS_SIZE, SZ_4K))
51 #define VDPU382_RPS_ALIGNED_SIZE (MPP_ALIGN(VDPU382_RPS_SIZE, SZ_4K))
52 #define VDPU382_SCALING_LIST_ALIGNED_SIZE (MPP_ALIGN(VDPU382_SCALING_LIST_SIZE, SZ_4K))
568 RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (ver_virstride + 16) / 16, SZ_4K); in set_registers()
H A Dhal_h264d_vdpu383.c31 #define VDPU383_CABAC_TAB_ALIGNED_SIZE (MPP_ALIGN(VDPU383_CABAC_TAB_SIZE, SZ_4K))
33 #define VDPU383_SPSPPS_ALIGNED_SIZE (MPP_ALIGN(VDPU383_SPSPPS_SIZE, SZ_4K))
34 #define VDPU383_RPS_ALIGNED_SIZE (MPP_ALIGN(VDPU383_RPS_SIZE, SZ_4K))
35 #define VDPU383_SCALING_LIST_ALIGNED_SIZE (MPP_ALIGN(VDPU383_SCALING_LIST_SIZE, SZ_4K))
H A Dhal_h264d_vdpu384a.c30 #define VDPU384A_SPSPPS_ALIGNED_SIZE (MPP_ALIGN(VDPU384A_SPSPPS_SIZE, SZ_4K))
31 #define VDPU384A_SCALING_LIST_ALIGNED_SIZE (MPP_ALIGN(VDPU384A_SCALING_LIST_SIZE, SZ_4K))
/rockchip-linux_mpp/osal/
H A Dmpp_allocator.c175 if (p->os_api.open(&p->ctx, SZ_4K, flags)) in mpp_allocator_get()
/rockchip-linux_mpp/mpp/hal/rkdec/vp9d/
H A Dhal_vp9d_vdpu34x.c39 #define PROB_SIZE_ALIGN_TO_4K MPP_ALIGN(PROB_SIZE, SZ_4K)
40 #define COUNT_SIZE_ALIGN_TO_4K MPP_ALIGN(COUNT_SIZE, SZ_4K)
41 #define MAX_SEGMAP_SIZE_ALIGN_TO_4K MPP_ALIGN(MAX_SEGMAP_SIZE, SZ_4K)
633 RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (h + 16) / 16, SZ_4K); in hal_vp9d_vdpu34x_gen_regs()
688 RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (h + 16) / 16, SZ_4K); in hal_vp9d_vdpu34x_gen_regs()
H A Dhal_vp9d_vdpu382.c39 #define PROB_SIZE_ALIGN_TO_4K MPP_ALIGN(PROB_SIZE, SZ_4K)
40 #define COUNT_SIZE_ALIGN_TO_4K MPP_ALIGN(COUNT_SIZE, SZ_4K)
41 #define MAX_SEGMAP_SIZE_ALIGN_TO_4K MPP_ALIGN(MAX_SEGMAP_SIZE, SZ_4K)
643 RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (h + 16) / 16, SZ_4K); in hal_vp9d_vdpu382_gen_regs()
698 RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (h + 16) / 16, SZ_4K); in hal_vp9d_vdpu382_gen_regs()
/rockchip-linux_mpp/mpp/vproc/iep/test/
H A Diep_test.c513 size_t src_size = MPP_ALIGN(info.src_size, SZ_4K); in main()
514 size_t dst_size = MPP_ALIGN(info.dst_size, SZ_4K); in main()
/rockchip-linux_mpp/mpp/hal/rkdec/h265d/
H A Dhal_h265d_vdpu382.c85 #define CABAC_TAB_ALIGEND_SIZE (MPP_ALIGN(27456, SZ_4K))
86 #define SPSPPS_ALIGNED_SIZE (MPP_ALIGN(112 * 64, SZ_4K))
87 #define RPS_ALIGEND_SIZE (MPP_ALIGN(400 * 8, SZ_4K))
88 #define SCALIST_ALIGNED_SIZE (MPP_ALIGN(81 * 1360, SZ_4K))
748 RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (ver_virstride + 64) / 16, SZ_4K); in hal_h265d_vdpu382_gen_regs()
H A Dhal_h265d_vdpu34x.c87 #define CABAC_TAB_ALIGEND_SIZE (MPP_ALIGN(27456, SZ_4K))
88 #define SPSPPS_ALIGNED_SIZE (MPP_ALIGN(112 * 64, SZ_4K))
89 #define RPS_ALIGEND_SIZE (MPP_ALIGN(400 * 8, SZ_4K))
90 #define SCALIST_ALIGNED_SIZE (MPP_ALIGN(81 * 1360, SZ_4K))
959 RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (ver_virstride + 64) / 16, SZ_4K); in hal_h265d_vdpu34x_gen_regs()
H A Dhal_h265d_vdpu383.c58 #define CABAC_TAB_ALIGEND_SIZE (MPP_ALIGN(27456, SZ_4K))
59 #define SPSPPS_ALIGNED_SIZE (MPP_ALIGN(176, SZ_4K))
60 #define RPS_ALIGEND_SIZE (MPP_ALIGN(400 * 8, SZ_4K))
61 #define SCALIST_ALIGNED_SIZE (MPP_ALIGN(81 * 1360, SZ_4K))
/rockchip-linux_mpp/kmpp/base/test/
H A Dkmpp_obj_test.c239 rk_u32 sizes[] = {512, SZ_4K, SZ_16K, SZ_128K, SZ_256K, SZ_1M, SZ_4M, SZ_16M}; in kmpp_shm_test()
/rockchip-linux_mpp/osal/inc/
H A Dmpp_common.h165 #define SZ_4K (SZ_1K*4) macro
/rockchip-linux_mpp/mpp/hal/rkdec/avs2d/
H A Dhal_avs2d_rkv.c40 #define AVS2_RKV_SHPH_ALIGNED_SIZE (MPP_ALIGN(AVS2_RKV_SHPH_SIZE, SZ_4K))
41 #define AVS2_RKV_SCALIST_ALIGNED_SIZE (MPP_ALIGN(AVS2_RKV_SCALIST_SIZE, SZ_4K))
357 RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (ver_virstride + 16) / 16, SZ_4K); in fill_registers()
H A Dhal_avs2d_vdpu382.c40 #define AVS2_RKV_SHPH_ALIGNED_SIZE (MPP_ALIGN(AVS2_RKV_SHPH_SIZE, SZ_4K))
41 #define AVS2_RKV_SCALIST_ALIGNED_SIZE (MPP_ALIGN(AVS2_RKV_SCALIST_SIZE, SZ_4K))
413 RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (ver_virstride + 16) / 16, SZ_4K); in fill_registers()
H A Dhal_avs2d_vdpu383.c32 #define AVS2_383_SHPH_ALIGNED_SIZE (MPP_ALIGN(AVS2_383_SHPH_SIZE, SZ_4K))
33 #define AVS2_383_SCALIST_ALIGNED_SIZE (MPP_ALIGN(AVS2_383_SCALIST_SIZE, SZ_4K))
/rockchip-linux_mpp/mpp/codec/
H A Dmpp_enc_v2.c141 size_t size = SZ_4K; in mpp_enc_init_v2()
/rockchip-linux_mpp/mpp/hal/vpu/vp8e/
H A Dhal_vp8e_base.c1227 MPP_ALIGN(mb_total * (16 * 16), SZ_4K) + SZ_4K); in alloc_buffer()
1237 MPP_ALIGN(mb_total * (2 * 8 * 8), SZ_4K) + SZ_4K); in alloc_buffer()
/rockchip-linux_mpp/mpp/legacy/
H A Dvpu_api_legacy.cpp1285 size_t buffer = MPP_ALIGN(length, SZ_4K); in encode()
1505 aEncOut->data = mpp_calloc(RK_U8, MPP_ALIGN(length + 16, SZ_4K)); in encoder_getstream()
/rockchip-linux_mpp/test/
H A Dmpi_rc2_test.c848 RK_U32 buf_size = MPP_ALIGN(len, SZ_4K); in mpi_rc_enc()
H A Dmpi_enc_mt_test.c250 p->header_size = MPP_ALIGN(MPP_ALIGN(p->width, 16) * MPP_ALIGN(p->height, 16) / 16, SZ_4K); in mt_test_ctx_init()

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