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Searched refs:OFFSET_CODEC_ADDR_REGS (Results 1 – 18 of 18) sorted by relevance

/rockchip-linux_mpp/mpp/hal/rkdec/inc/
H A Dvdpu34x_com.h27 #define OFFSET_CODEC_ADDR_REGS (160 * sizeof(RK_U32)) macro
H A Dvdpu383_com.h16 #define OFFSET_CODEC_ADDR_REGS (168 * sizeof(RK_U32)) macro
H A Dvdpu384a_com.h16 #define OFFSET_CODEC_ADDR_REGS (168 * sizeof(RK_U32)) macro
H A Dvdpu382_com.h27 #define OFFSET_CODEC_ADDR_REGS (160 * sizeof(RK_U32)) macro
/rockchip-linux_mpp/mpp/hal/rkdec/avs2d/
H A Dhal_avs2d_rkv.c759 …fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", (RK_U32)(i + OFFSET_CODEC_ADDR_REGS / sizeof(RK_U32)… in hal_avs2d_rkv_dump_reg_write()
861 wr_cfg.offset = OFFSET_CODEC_ADDR_REGS; in hal_avs2d_rkv_start()
H A Dhal_avs2d_vdpu382.c825 …fprintf(fp_reg, "Write reg[%03d] : 0x%08x\n", (RK_U32)(i + OFFSET_CODEC_ADDR_REGS / sizeof(RK_U32)… in hal_avs2d_vdpu382_dump_reg_write()
927 wr_cfg.offset = OFFSET_CODEC_ADDR_REGS; in hal_avs2d_vdpu382_start()
H A Dhal_avs2d_vdpu383.c765 wr_cfg.offset = OFFSET_CODEC_ADDR_REGS; in hal_avs2d_vdpu383_start()
/rockchip-linux_mpp/mpp/hal/rkdec/h264d/
H A Dhal_h264d_vdpu34x.c1057 wr_cfg.offset = OFFSET_CODEC_ADDR_REGS; in vdpu34x_h264d_start()
H A Dhal_h264d_vdpu384a.c917 wr_cfg.offset = OFFSET_CODEC_ADDR_REGS; in vdpu384a_h264d_start()
H A Dhal_h264d_vdpu383.c971 wr_cfg.offset = OFFSET_CODEC_ADDR_REGS; in vdpu383_h264d_start()
H A Dhal_h264d_vdpu382.c1111 wr_cfg.offset = OFFSET_CODEC_ADDR_REGS; in vdpu382_h264d_start()
/rockchip-linux_mpp/mpp/hal/rkdec/vp9d/
H A Dhal_vp9d_vdpu34x.c937 wr_cfg.offset = OFFSET_CODEC_ADDR_REGS; in hal_vp9d_vdpu34x_start()
H A Dhal_vp9d_vdpu382.c971 wr_cfg.offset = OFFSET_CODEC_ADDR_REGS; in hal_vp9d_vdpu382_start()
H A Dhal_vp9d_vdpu383.c1177 wr_cfg.offset = OFFSET_CODEC_ADDR_REGS; in hal_vp9d_vdpu383_start()
/rockchip-linux_mpp/mpp/hal/rkdec/h265d/
H A Dhal_h265d_vdpu382.c1017 wr_cfg.offset = OFFSET_CODEC_ADDR_REGS; in hal_h265d_vdpu382_start()
H A Dhal_h265d_vdpu384a.c1239 wr_cfg.offset = OFFSET_CODEC_ADDR_REGS; in hal_h265d_vdpu384a_start()
H A Dhal_h265d_vdpu34x.c1224 wr_cfg.offset = OFFSET_CODEC_ADDR_REGS; in hal_h265d_vdpu34x_start()
H A Dhal_h265d_vdpu383.c1301 wr_cfg.offset = OFFSET_CODEC_ADDR_REGS; in hal_h265d_vdpu383_start()