Searched refs:zq (Results 1 – 14 of 14) sorted by relevance
| /rk3399_rockchip-uboot/arch/arm/mach-uniphier/dram/ |
| H A D | cmd_ddrmphy.c | 94 int phy, zq, i; in zq_dump() local
103 for (zq = 0; zq < param->phy[phy].nr_zq; zq++) { in zq_dump()
104 printf("PHY%dZQ%d:", phy, zq); in zq_dump()
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| H A D | umc-pxs2.c | 147 int zq, dx; in ddrphy_init() local
207 for (zq = 0; zq < 4; zq++) { in ddrphy_init()
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| /rk3399_rockchip-uboot/board/sunxi/ |
| H A D | dram_sun4i_auto.c | 11 .zq = CONFIG_DRAM_ZQ,
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| H A D | dram_sun5i_auto.c | 14 .zq = CONFIG_DRAM_ZQ,
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| /rk3399_rockchip-uboot/arch/arm/mach-sunxi/ |
| H A D | dram_sun8i_a23.c | 33 .zq = CONFIG_DRAM_ZQ,
230 writel((dram_para.zq >> 8) & 0xff, &mctl_phy->zqcr1); in mctl_init()
237 writel(dram_para.zq & 0xff, &mctl_phy->zqcr1); in mctl_init()
247 writel(dram_para.zq & 0xff, &mctl_phy->zqcr1); in mctl_init()
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| H A D | dram_sunxi_dw.c | 308 u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf; in mctl_h3_zq_calibration_quirk() local
310 writel((zq << 20) | (zq << 16) | (zq << 12) | in mctl_h3_zq_calibration_quirk()
311 (zq << 8) | (zq << 4) | (zq << 0), in mctl_h3_zq_calibration_quirk()
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| H A D | dram_sun9i.c | 699 clrsetbits_le32(&mctl_phy->zq[0].pr, 0xff, in mctl_channel_init()
701 clrsetbits_le32(&mctl_phy->zq[1].pr, 0xff, in mctl_channel_init()
703 clrsetbits_le32(&mctl_phy->zq[2].pr, 0xff, in mctl_channel_init()
729 writel(0x04058D02, &mctl_phy->zq[0].cr); /* CK/CA */ in mctl_channel_init()
730 writel(0x04058D02, &mctl_phy->zq[1].cr); /* DX0/DX1 */ in mctl_channel_init()
731 writel(0x04058D02, &mctl_phy->zq[2].cr); /* DX2/DX3 */ in mctl_channel_init()
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| H A D | dram_sun4i.c | 511 static void mctl_set_impedance(u32 zq, bool odt_en) in mctl_set_impedance() argument
515 u32 zprog = zq & 0xFF, zdata = (zq >> 8) & 0xFFFFF; in mctl_set_impedance()
623 mctl_set_impedance(para->zq, para->odt_en); in dramc_init_helper()
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| H A D | Kconfig | 297 int "sunxi dram zq value"
305 Set the dram zq value.
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| /rk3399_rockchip-uboot/arch/arm/mach-omap2/ |
| H A D | emif-common.c | 681 u32 zq = 0, val = 0; in get_zq_config_reg() local
690 zq |= val << EMIF_REG_ZQ_REFINTERVAL_SHIFT; in get_zq_config_reg()
692 zq |= (REG_ZQ_ZQCL_MULT - 1) << EMIF_REG_ZQ_ZQCL_MULT_SHIFT; in get_zq_config_reg()
694 zq |= (REG_ZQ_ZQINIT_MULT - 1) << EMIF_REG_ZQ_ZQINIT_MULT_SHIFT; in get_zq_config_reg()
696 zq |= REG_ZQ_SFEXITEN_ENABLE << EMIF_REG_ZQ_SFEXITEN_SHIFT; in get_zq_config_reg()
706 zq |= REG_ZQ_DUALCALEN_DISABLE << EMIF_REG_ZQ_DUALCALEN_SHIFT; in get_zq_config_reg()
708 zq |= REG_ZQ_CS0EN_ENABLE << EMIF_REG_ZQ_CS0EN_SHIFT; in get_zq_config_reg()
710 zq |= (cs1_device ? 1 : 0) << EMIF_REG_ZQ_CS1EN_SHIFT; in get_zq_config_reg()
712 return zq; in get_zq_config_reg()
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-sunxi/ |
| H A D | dram_sun4i.h | 77 u32 zq; member
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| H A D | dram_sun9i.h | 141 } zq[4]; /* 0x240, 0x250, 0x260, 0x270 */ member
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| H A D | dram_sun8i_a23.h | 20 u32 zq; member
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| /rk3399_rockchip-uboot/drivers/ram/rockchip/ |
| H A D | sdram_rv1126.c | 2470 static int check_lp4_rzqi_value(struct dram_info *dram, u32 cs, u32 byte, u32 zq, u32 dramtype) in check_lp4_rzqi_value() argument
2477 printdec(zq); in check_lp4_rzqi_value()
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