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Searched refs:wdog (Results 1 – 25 of 25) sorted by relevance

/rk3399_rockchip-uboot/drivers/watchdog/
H A Dulp_wdog.c48 struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; in hw_watchdog_set_timeout() local
50 writel(val, &wdog->toval); in hw_watchdog_set_timeout()
55 struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; in hw_watchdog_reset() local
57 writel(REFRESH_WORD0, &wdog->cnt); in hw_watchdog_reset()
58 writel(REFRESH_WORD1, &wdog->cnt); in hw_watchdog_reset()
64 struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; in hw_watchdog_init() local
66 writel(UNLOCK_WORD0, &wdog->cnt); in hw_watchdog_init()
67 writel(UNLOCK_WORD1, &wdog->cnt); in hw_watchdog_init()
69 val = readb(&wdog->cs2); in hw_watchdog_init()
71 writeb(val, &wdog->cs2); in hw_watchdog_init()
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H A Dimx_watchdog.c16 struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; in hw_watchdog_reset() local
18 writew(0x5555, &wdog->wsr); in hw_watchdog_reset()
19 writew(0xaaaa, &wdog->wsr); in hw_watchdog_reset()
24 struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; in hw_watchdog_init() local
37 WCR_WDA | SET_WCR_WT(timeout), &wdog->wcr); in hw_watchdog_init()
44 struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; in reset_cpu() local
46 clrsetbits_le16(&wdog->wcr, WCR_WT_MSK, WCR_WDE); in reset_cpu()
48 writew(0x5555, &wdog->wsr); in reset_cpu()
49 writew(0xaaaa, &wdog->wsr); /* load minimum 1/2 second timeout */ in reset_cpu()
/rk3399_rockchip-uboot/arch/arm/mach-sunxi/
H A Dboard.c280 static const struct sunxi_wdog *wdog = in reset_cpu() local
281 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; in reset_cpu()
284 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); in reset_cpu()
285 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl); in reset_cpu()
289 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); in reset_cpu()
292 static const struct sunxi_wdog *wdog = in reset_cpu()
293 ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; in reset_cpu()
296 writel(WDT_CFG_RESET, &wdog->cfg); in reset_cpu()
297 writel(WDT_MODE_EN, &wdog->mode); in reset_cpu()
298 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl); in reset_cpu()
/rk3399_rockchip-uboot/drivers/mmc/
H A Ddavinci_mmc.c61 uint wdog = WATCHDOG_COUNT; in dmmc_wait_fifo_status() local
63 while (--wdog && ((get_val(&regs->mmcst1) & status) != status)) in dmmc_wait_fifo_status()
69 if (wdog == 0) in dmmc_wait_fifo_status()
78 uint wdog = WATCHDOG_COUNT; in dmmc_busy_wait() local
80 while (--wdog && (get_val(&regs->mmcst1) & MMCST1_BUSY)) in dmmc_busy_wait()
83 if (wdog == 0) in dmmc_busy_wait()
93 uint wdog = WATCHDOG_COUNT; in dmmc_check_status() local
96 while (wdog--) { in dmmc_check_status()
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-sunxi/
H A Dtimer.h71 struct sunxi_wdog wdog; /* 0x90 */ member
82 struct sunxi_wdog wdog[5]; /* We have 5 watchdogs */ member
/rk3399_rockchip-uboot/board/warp7/
H A Dwarp7.c188 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; in board_late_init() local
192 set_wdog_reset(wdog); in board_late_init()
198 clrsetbits_le16(&wdog->wcr, 0, 0x10); in board_late_init()
/rk3399_rockchip-uboot/arch/arm/mach-davinci/
H A Ddm365_lowlevel.c267 struct davinci_timer *wdog = in dm365_por_reset() local
276 writel(DV_WDT_ENABLE_SYS_RESET, &wdog->na1); in dm365_por_reset()
277 writel(DV_WDT_TRIGGER_SYS_RESET, &wdog->na2); in dm365_por_reset()
285 struct davinci_timer *wdog = in dm365_wdt_reset() local
297 writel(DV_WDT_ENABLE_SYS_RESET, &wdog->na1); in dm365_wdt_reset()
298 writel(DV_WDT_TRIGGER_SYS_RESET, &wdog->na2); in dm365_wdt_reset()
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-mx7/
H A Dsys_proto.h9 void set_wdog_reset(struct wdog_regs *wdog);
/rk3399_rockchip-uboot/arch/arm/mach-imx/mx7/
H A Dsoc.c350 void set_wdog_reset(struct wdog_regs *wdog) in set_wdog_reset() argument
352 u32 reg = readw(&wdog->wcr); in set_wdog_reset()
358 reg = readw(&wdog->wcr); in set_wdog_reset()
365 writew(reg, &wdog->wcr); in set_wdog_reset()
/rk3399_rockchip-uboot/arch/arm/mach-bcm283x/include/mach/
H A Dwdog.h20 u32 wdog; member
/rk3399_rockchip-uboot/board/technexion/pico-imx7d/
H A Dpico-imx7d.c264 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; in board_late_init() local
268 set_wdog_reset(wdog); in board_late_init()
274 clrsetbits_le16(&wdog->wcr, 0, 0x10); in board_late_init()
/rk3399_rockchip-uboot/arch/m68k/cpu/mcf523x/
H A Dcpu_init.c41 wdog_t *wdog = (wdog_t *) MMAP_WDOG; in cpu_init_f() local
46 out_be16(&wdog->cr, 0); in cpu_init_f()
/rk3399_rockchip-uboot/board/freescale/mx7dsabresd/
H A Dmx7dsabresd.c369 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; in board_late_init() local
373 set_wdog_reset(wdog); in board_late_init()
379 clrsetbits_le16(&wdog->wcr, 0, 0x10); in board_late_init()
/rk3399_rockchip-uboot/arch/arm/mach-bcm283x/
H A Dreset.c50 writel(BCM2835_WDOG_PASSWORD | timeout, &wdog_regs->wdog); in reset_cpu()
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/ls102xa/
H A Dcpu.c373 struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; in reset_cpu() local
375 clrbits_be16(&wdog->wcr, WCR_SRS); in reset_cpu()
/rk3399_rockchip-uboot/arch/m68k/cpu/mcf532x/
H A Dcpu_init.c212 wdog_t *wdog = (wdog_t *) MMAP_WDOG; in cpu_init_f() local
215 out_be16(&wdog->cr, 0); in cpu_init_f()
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dimx7s.dtsi409 wdog1: wdog@30280000 {
416 wdog2: wdog@30290000 {
424 wdog3: wdog@302a0000 {
432 wdog4: wdog@302b0000 {
H A Dimx7ulp.dtsi347 wdog1: wdog@403D0000 {
362 wdog2: wdog@40430000 {
H A Dls1021a.dtsi309 clock-names = "wdog-en";
H A Dimx6sx.dtsi534 wdog1: wdog@020bc000 {
541 wdog2: wdog@020c0000 {
1197 wdog3: wdog@02288000 {
H A Dimx6sll.dtsi476 wdog1: wdog@020bc000 {
483 wdog2: wdog@020c0000 {
H A Dimx6sl.dtsi489 wdog1: wdog@020bc000 {
496 wdog2: wdog@020c0000 {
H A Dimx6ul.dtsi493 wdog1: wdog@020bc000 {
500 wdog2: wdog@020c0000 {
H A Dimx6ull.dtsi585 wdog1: wdog@020bc000 {
592 wdog2: wdog@020c0000 {
H A Dimx6qdl.dtsi595 wdog1: wdog@020bc000 {
602 wdog2: wdog@020c0000 {