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/rk3399_rockchip-uboot/arch/arm/include/asm/arch-tegra/
H A Dpmc.h13 uint pmc_cntrl; /* _CNTRL_0, offset 00 */
14 uint pmc_sec_disable; /* _SEC_DISABLE_0, offset 04 */
15 uint pmc_pmc_swrst; /* _PMC_SWRST_0, offset 08 */
16 uint pmc_wake_mask; /* _WAKE_MASK_0, offset 0C */
17 uint pmc_wake_lvl; /* _WAKE_LVL_0, offset 10 */
18 uint pmc_wake_status; /* _WAKE_STATUS_0, offset 14 */
19 uint pmc_sw_wake_status; /* _SW_WAKE_STATUS_0, offset 18 */
20 uint pmc_dpd_pads_oride; /* _DPD_PADS_ORIDE_0, offset 1C */
21 uint pmc_dpd_sample; /* _DPD_PADS_SAMPLE_0, offset 20 */
22 uint pmc_dpd_enable; /* _DPD_PADS_ENABLE_0, offset 24 */
[all …]
H A Ddc.h16 uint gen_incr_syncpt; /* _CMD_GENERAL_INCR_SYNCPT_0 */
17 uint gen_incr_syncpt_ctrl; /* _CMD_GENERAL_INCR_SYNCPT_CNTRL_0 */
18 uint gen_incr_syncpt_err; /* _CMD_GENERAL_INCR_SYNCPT_ERROR_0 */
20 uint reserved0[5]; /* reserved_0[5] */
23 uint win_a_incr_syncpt; /* _CMD_WIN_A_INCR_SYNCPT_0 */
24 uint win_a_incr_syncpt_ctrl; /* _CMD_WIN_A_INCR_SYNCPT_CNTRL_0 */
25 uint win_a_incr_syncpt_err; /* _CMD_WIN_A_INCR_SYNCPT_ERROR_0 */
27 uint reserved1[5]; /* reserved_1[5] */
30 uint win_b_incr_syncpt; /* _CMD_WIN_B_INCR_SYNCPT_0 */
31 uint win_b_incr_syncpt_ctrl; /* _CMD_WIN_B_INCR_SYNCPT_CNTRL_0 */
[all …]
H A Dusb.h14 uint id;
15 uint reserved0;
16 uint host;
17 uint device;
20 uint txbuf;
21 uint rxbuf;
22 uint reserved1[2];
25 uint reserved2[56];
30 uint hcs_params;
31 uint hcc_params;
[all …]
H A Dclk_rst.h13 uint pll_base; /* the control register */
15 uint pll_out[2];
16 uint pll_misc; /* other misc things */
21 uint pll_base; /* the control register */
22 uint pll_misc; /* other misc things */
26 uint pllm_base; /* the control register */
27 uint pllm_out; /* output control */
28 uint pllm_misc1; /* misc1 */
29 uint pllm_misc2; /* misc2 */
34 uint set;
[all …]
H A Duart.h13 uint uart_thr_dlab_0; /* UART_THR_DLAB_0_0, offset 00 */
14 uint uart_ier_dlab_0; /* UART_IER_DLAB_0_0, offset 04 */
15 uint uart_iir_fcr; /* UART_IIR_FCR_0, offset 08 */
16 uint uart_lcr; /* UART_LCR_0, offset 0C */
17 uint uart_mcr; /* UART_MCR_0, offset 10 */
18 uint uart_lsr; /* UART_LSR_0, offset 14 */
19 uint uart_msr; /* UART_MSR_0, offset 18 */
20 uint uart_spr; /* UART_SPR_0, offset 1C */
21 uint uart_irda_csr; /* UART_IRDA_CSR_0, offset 20 */
22 uint uart_reserved[6]; /* Reserved, unused, offset 24-38*/
[all …]
H A Dscu.h13 uint scu_ctrl; /* SCU Control Register, offset 00 */
14 uint scu_cfg; /* SCU Config Register, offset 04 */
15 uint scu_cpu_pwr_stat; /* SCU CPU Power Status Register, offset 08 */
16 uint scu_inv_all; /* SCU Invalidate All Register, offset 0C */
17 uint scu_reserved0[12]; /* reserved, offset 10-3C */
18 uint scu_filt_start; /* SCU Filtering Start Address Reg, offset 40 */
19 uint scu_filt_end; /* SCU Filtering End Address Reg, offset 44 */
20 uint scu_reserved1[2]; /* reserved, offset 48-4C */
21 uint scu_acc_ctl; /* SCU Access Control Register, offset 50 */
22 uint scu_ns_acc_ctl; /* SCU Non-secure Access Cntrl Reg, offset 54 */
/rk3399_rockchip-uboot/arch/powerpc/include/asm/
H A Dimmap_86xx.h21 uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */
23 uint altcbar; /* 0x8 - Alternate Configuration Base Address Register */
25 uint altcar; /* 0x10 - Alternate Configuration Attribute Register */
27 uint bptr; /* 0x20 - Boot Page Translation Register */
29 uint lawbar0; /* 0xc08 - Local Access Window 0 Base Address Register */
31 uint lawar0; /* 0xc10 - Local Access Window 0 Attributes Register */
33 uint lawbar1; /* 0xc28 - Local Access Window 1 Base Address Register */
35 uint lawar1; /* 0xc30 - Local Access Window 1 Attributes Register */
37 uint lawbar2; /* 0xc48 - Local Access Window 2 Base Address Register */
39 uint lawar2; /* 0xc50 - Local Access Window 2 Attributes Register */
[all …]
H A Dcpm_85xx.h21 #define CPM_CR_RST ((uint)0x80000000)
22 #define CPM_CR_PAGE ((uint)0x7c000000)
23 #define CPM_CR_SBLOCK ((uint)0x03e00000)
24 #define CPM_CR_FLG ((uint)0x00010000)
25 #define CPM_CR_MCN ((uint)0x00003fc0)
26 #define CPM_CR_OPCODE ((uint)0x0000000f)
78 #define CPM_DATAONLY_BASE ((uint)128)
79 #define CPM_DP_NOSPACE ((uint)0x7FFFFFFF)
81 #define CPM_FCC_SPECIAL_BASE ((uint)0x00009000)
82 #define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
[all …]
H A Dimmap_8xx.h18 uint sc_siumcr;
19 uint sc_sypcr;
20 uint sc_swt;
23 uint sc_sipend;
24 uint sc_simask;
25 uint sc_siel;
26 uint sc_sivec;
27 uint sc_tesr;
29 uint sc_sdcr;
36 uint pcmc_pbr0;
[all …]
H A Dcpm_8xx.h63 #define BD_IIC_START ((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */
75 uint cbd_bufaddr; /* Buffer address in host memory */
95 #define PROFF_SCC1 ((uint)0x0000)
96 #define PROFF_IIC ((uint)0x0080)
97 #define PROFF_REVNUM ((uint)0x00b0)
98 #define PROFF_SCC2 ((uint)0x0100)
99 #define PROFF_SPI ((uint)0x0180)
100 #define PROFF_SCC3 ((uint)0x0200)
101 #define PROFF_SMC1 ((uint)0x0280)
102 #define PROFF_SCC4 ((uint)0x0300)
[all …]
H A Dfsl_dma.h16 uint mr; /* DMA mode register */
32 uint sr; /* DMA status register */
37 uint cdar; /* DMA current descriptor address register */
39 uint sar; /* DMA source address register */
41 uint dar; /* DMA destination address register */
43 uint bcr; /* DMA byte count register */
44 uint ndar; /* DMA next descriptor address register */
45 uint gsr; /* DMA general status register (DMA3 ONLY!) */
50 uint mr; /* DMA mode register */
71 uint sr; /* DMA status register */
[all …]
/rk3399_rockchip-uboot/include/
H A Dlcdvideo.h11 #define LCCR_BNUM ((uint)0xfffe0000)
12 #define LCCR_EIEN ((uint)0x00010000)
13 #define LCCR_IEN ((uint)0x00008000)
14 #define LCCR_IRQL ((uint)0x00007000)
15 #define LCCR_CLKP ((uint)0x00000800)
16 #define LCCR_OEP ((uint)0x00000400)
17 #define LCCR_HSP ((uint)0x00000200)
18 #define LCCR_VSP ((uint)0x00000100)
19 #define LCCR_DP ((uint)0x00000080)
20 #define LCCR_BPIX ((uint)0x00000060)
[all …]
H A Dbitfield.h43 static inline uint bitfield_mask(uint shift, uint width) in bitfield_mask()
49 static inline uint bitfield_extract(uint reg_val, uint shift, uint width) in bitfield_extract()
58 static inline uint bitfield_replace(uint reg_val, uint shift, uint width, in bitfield_replace()
59 uint bitfield_val) in bitfield_replace()
61 uint mask = bitfield_mask(shift, width); in bitfield_replace()
67 static inline uint bitfield_shift(uint mask) in bitfield_shift()
73 static inline uint bitfield_extract_by_mask(uint reg_val, uint mask) in bitfield_extract_by_mask()
75 uint shift = bitfield_shift(mask); in bitfield_extract_by_mask()
84 static inline uint bitfield_replace_by_mask(uint reg_val, uint mask, in bitfield_replace_by_mask()
85 uint bitfield_val) in bitfield_replace_by_mask()
[all …]
H A Dvideo_console.h67 int (*putc_xy)(struct udevice *dev, uint x_frac, uint y, char ch);
78 int (*move_rows)(struct udevice *dev, uint rowdst, uint rowsrc,
79 uint count);
91 int (*set_row)(struct udevice *dev, uint row, int clr);
135 int vidconsole_putc_xy(struct udevice *dev, uint x, uint y, char ch);
146 int vidconsole_move_rows(struct udevice *dev, uint rowdst, uint rowsrc,
147 uint count);
159 int vidconsole_set_row(struct udevice *dev, uint row, int clr);
H A Dpwm.h25 int (*set_config)(struct udevice *dev, uint channel, uint period_ns,
26 uint duty_ns);
36 int (*set_enable)(struct udevice *dev, uint channel, bool enable);
45 int (*set_invert)(struct udevice *dev, uint channel, bool polarity);
59 int pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
60 uint duty_ns);
70 int pwm_set_enable(struct udevice *dev, uint channel, bool enable);
80 int pwm_set_invert(struct udevice *dev, uint channel, bool polarity);
H A Di2c.h52 uint chip_addr;
53 uint offset_len;
54 uint flags;
100 uint addr;
101 uint flags;
102 uint len;
117 uint nmsgs;
137 int dm_i2c_read(struct udevice *dev, uint offset, uint8_t *buffer, int len);
151 int dm_i2c_write(struct udevice *dev, uint offset, const uint8_t *buffer,
167 int dm_i2c_probe(struct udevice *bus, uint chip_addr, uint chip_flags,
[all …]
H A Ddebug_uart.h97 void printhex2(uint value);
104 void printhex4(uint value);
111 void printhex8(uint value);
118 void printdec(uint value);
185 static inline void printhex1(uint digit) \
191 static inline void printhex(uint value, int digits) \
197 void printhex2(uint value) \
202 void printhex4(uint value) \
207 void printhex8(uint value) \
212 void printdec(uint value) \
H A Dsmsc_lpc47m.h29 void lpc47m_enable_serial(uint dev, uint iobase, uint irq);
39 void lpc47m_enable_kbc(uint dev, uint irq0, uint irq1);
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-tegra30/
H A Dgpio.h21 uint gpio_config[TEGRA_GPIO_PORTS];
22 uint gpio_dir_out[TEGRA_GPIO_PORTS];
23 uint gpio_out[TEGRA_GPIO_PORTS];
24 uint gpio_in[TEGRA_GPIO_PORTS];
25 uint gpio_int_status[TEGRA_GPIO_PORTS];
26 uint gpio_int_enable[TEGRA_GPIO_PORTS];
27 uint gpio_int_level[TEGRA_GPIO_PORTS];
28 uint gpio_int_clear[TEGRA_GPIO_PORTS];
29 uint gpio_masked_config[TEGRA_GPIO_PORTS];
30 uint gpio_masked_dir_out[TEGRA_GPIO_PORTS];
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-tegra124/
H A Dgpio.h22 uint gpio_config[TEGRA_GPIO_PORTS];
23 uint gpio_dir_out[TEGRA_GPIO_PORTS];
24 uint gpio_out[TEGRA_GPIO_PORTS];
25 uint gpio_in[TEGRA_GPIO_PORTS];
26 uint gpio_int_status[TEGRA_GPIO_PORTS];
27 uint gpio_int_enable[TEGRA_GPIO_PORTS];
28 uint gpio_int_level[TEGRA_GPIO_PORTS];
29 uint gpio_int_clear[TEGRA_GPIO_PORTS];
30 uint gpio_masked_config[TEGRA_GPIO_PORTS];
31 uint gpio_masked_dir_out[TEGRA_GPIO_PORTS];
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-tegra210/
H A Dgpio.h22 uint gpio_config[TEGRA_GPIO_PORTS];
23 uint gpio_dir_out[TEGRA_GPIO_PORTS];
24 uint gpio_out[TEGRA_GPIO_PORTS];
25 uint gpio_in[TEGRA_GPIO_PORTS];
26 uint gpio_int_status[TEGRA_GPIO_PORTS];
27 uint gpio_int_enable[TEGRA_GPIO_PORTS];
28 uint gpio_int_level[TEGRA_GPIO_PORTS];
29 uint gpio_int_clear[TEGRA_GPIO_PORTS];
30 uint gpio_masked_config[TEGRA_GPIO_PORTS];
31 uint gpio_masked_dir_out[TEGRA_GPIO_PORTS];
[all …]
/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc85xx/
H A Dcommproc.c34 #define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
63 uint
64 m8560_cpm_dpalloc(uint size, uint align) in m8560_cpm_dpalloc()
67 uint retloc; in m8560_cpm_dpalloc()
68 uint align_mask, off; in m8560_cpm_dpalloc()
69 uint savebase; in m8560_cpm_dpalloc()
97 uint
98 m8560_cpm_hostalloc(uint size, uint align) in m8560_cpm_hostalloc()
121 m8560_cpm_setbrg(uint brg, uint rate) in m8560_cpm_setbrg()
124 volatile uint *bp; in m8560_cpm_setbrg()
[all …]
/rk3399_rockchip-uboot/drivers/bios_emulator/include/x86emu/
H A Ddecode.h63 u8 fetch_data_byte (uint offset);
64 u8 fetch_data_byte_abs (uint segment, uint offset);
65 u16 fetch_data_word (uint offset);
66 u16 fetch_data_word_abs (uint segment, uint offset);
67 u32 fetch_data_long (uint offset);
68 u32 fetch_data_long_abs (uint segment, uint offset);
69 void store_data_byte (uint offset, u8 val);
70 void store_data_byte_abs (uint segment, uint offset, u8 val);
71 void store_data_word (uint offset, u16 val);
72 void store_data_word_abs (uint segment, uint offset, u16 val);
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-tegra20/
H A Dgpio.h22 uint gpio_config[TEGRA_GPIO_PORTS];
23 uint gpio_dir_out[TEGRA_GPIO_PORTS];
24 uint gpio_out[TEGRA_GPIO_PORTS];
25 uint gpio_in[TEGRA_GPIO_PORTS];
26 uint gpio_int_status[TEGRA_GPIO_PORTS];
27 uint gpio_int_enable[TEGRA_GPIO_PORTS];
28 uint gpio_int_level[TEGRA_GPIO_PORTS];
29 uint gpio_int_clear[TEGRA_GPIO_PORTS];
/rk3399_rockchip-uboot/arch/m68k/include/asm/
H A Dimmap_5272.h35 uint sc_mbar;
38 uint sc_pmr;
41 uint sc_dir;
47 uint int_icr1;
48 uint int_icr2;
49 uint int_icr3;
50 uint int_icr4;
51 uint int_isr;
52 uint int_pitr;
53 uint int_piwr;
[all …]

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