1150c2493STom Warren /* 2150c2493STom Warren * (C) Copyright 2010,2011 3150c2493STom Warren * NVIDIA Corporation <www.nvidia.com> 4150c2493STom Warren * 5*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 6150c2493STom Warren */ 7150c2493STom Warren 8150c2493STom Warren #ifndef _SCU_H_ 9150c2493STom Warren #define _SCU_H_ 10150c2493STom Warren 11150c2493STom Warren /* ARM Snoop Control Unit (SCU) registers */ 12150c2493STom Warren struct scu_ctlr { 13150c2493STom Warren uint scu_ctrl; /* SCU Control Register, offset 00 */ 14150c2493STom Warren uint scu_cfg; /* SCU Config Register, offset 04 */ 15150c2493STom Warren uint scu_cpu_pwr_stat; /* SCU CPU Power Status Register, offset 08 */ 16150c2493STom Warren uint scu_inv_all; /* SCU Invalidate All Register, offset 0C */ 17150c2493STom Warren uint scu_reserved0[12]; /* reserved, offset 10-3C */ 18150c2493STom Warren uint scu_filt_start; /* SCU Filtering Start Address Reg, offset 40 */ 19150c2493STom Warren uint scu_filt_end; /* SCU Filtering End Address Reg, offset 44 */ 20150c2493STom Warren uint scu_reserved1[2]; /* reserved, offset 48-4C */ 21150c2493STom Warren uint scu_acc_ctl; /* SCU Access Control Register, offset 50 */ 22150c2493STom Warren uint scu_ns_acc_ctl; /* SCU Non-secure Access Cntrl Reg, offset 54 */ 23150c2493STom Warren }; 24150c2493STom Warren 25150c2493STom Warren #define SCU_CTRL_ENABLE (1 << 0) 26150c2493STom Warren 27150c2493STom Warren #endif /* SCU_H */ 28