1150c2493STom Warren /* 2150c2493STom Warren * (C) Copyright 2010,2011 3150c2493STom Warren * NVIDIA Corporation <www.nvidia.com> 4150c2493STom Warren * 5*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 6150c2493STom Warren */ 7150c2493STom Warren 8150c2493STom Warren #ifndef _UART_H_ 9150c2493STom Warren #define _UART_H_ 10150c2493STom Warren 11150c2493STom Warren /* UART registers */ 12150c2493STom Warren struct uart_ctlr { 13150c2493STom Warren uint uart_thr_dlab_0; /* UART_THR_DLAB_0_0, offset 00 */ 14150c2493STom Warren uint uart_ier_dlab_0; /* UART_IER_DLAB_0_0, offset 04 */ 15150c2493STom Warren uint uart_iir_fcr; /* UART_IIR_FCR_0, offset 08 */ 16150c2493STom Warren uint uart_lcr; /* UART_LCR_0, offset 0C */ 17150c2493STom Warren uint uart_mcr; /* UART_MCR_0, offset 10 */ 18150c2493STom Warren uint uart_lsr; /* UART_LSR_0, offset 14 */ 19150c2493STom Warren uint uart_msr; /* UART_MSR_0, offset 18 */ 20150c2493STom Warren uint uart_spr; /* UART_SPR_0, offset 1C */ 21150c2493STom Warren uint uart_irda_csr; /* UART_IRDA_CSR_0, offset 20 */ 22150c2493STom Warren uint uart_reserved[6]; /* Reserved, unused, offset 24-38*/ 23150c2493STom Warren uint uart_asr; /* UART_ASR_0, offset 3C */ 24150c2493STom Warren }; 25150c2493STom Warren 26150c2493STom Warren #define NVRM_PLLP_FIXED_FREQ_KHZ 216000 27150c2493STom Warren #define NV_DEFAULT_DEBUG_BAUD 115200 28150c2493STom Warren 29150c2493STom Warren #define UART_FCR_TRIGGER_3 0x30 /* Mask for trigger set at 3 */ 30150c2493STom Warren 31150c2493STom Warren #endif /* UART_H */ 32