Searched refs:tWTR (Results 1 – 10 of 10) sorted by relevance
| /rk3399_rockchip-uboot/arch/arm/mach-sunxi/ |
| H A D | dram_sun9i.c | 125 struct dram_sun9i_timing tWTR; member
388 const u32 tWTR = MAX(para->tWTR.ck, PS2CYCLES_ROUNDUP(para->tWTR.ps)); in mctl_channel_init() local
521 #define WR2PRE (MCTL_BL/2 + CWL + tWTR) in mctl_channel_init()
523 #define WR2RD (MCTL_BL/2 + CWL + tWTR) in mctl_channel_init()
645 (tRCD << 12) | (tRP << 8) | (tWTR << 4) | (tRTP << 0), in mctl_channel_init()
898 .tWTR = { .ck = 4, .ps = 7500 }, in sunxi_dram_init()
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| /rk3399_rockchip-uboot/arch/arm/mach-omap2/omap5/ |
| H A D | emif.c | 62 .tWTR = 2,
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| H A D | sdram.c | 639 .tWTR = 2,
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| /rk3399_rockchip-uboot/arch/arm/mach-omap2/omap4/ |
| H A D | emif.c | 85 .tWTR = 2,
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| H A D | sdram_elpida.c | 267 .tWTR = 2,
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| /rk3399_rockchip-uboot/board/buffalo/lsxl/ |
| H A D | kwbimage-lschl.cfg | 61 # bit19-16: 2, 3 cyle tWTR
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| H A D | kwbimage-lsxhl.cfg | 61 # bit19-16: 2, 3 cyle tWTR
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| /rk3399_rockchip-uboot/board/d-link/dns325/ |
| H A D | kwbimage.cfg | 58 # bit19-16: 2, 3 cyle tWTR
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| /rk3399_rockchip-uboot/arch/arm/include/asm/ |
| H A D | emif.h | 1131 u32 tWTR; member
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| /rk3399_rockchip-uboot/arch/arm/mach-omap2/ |
| H A D | emif-common.c | 601 val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1; in get_sdram_tim_1_reg()
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