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Searched refs:tRCD (Results 1 – 11 of 11) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/mach-omap2/omap4/
H A Demif.c28 .tRCD = 18,
52 .tRCD = 18,
81 .tRCD = 3,
H A Dsdram_elpida.c195 .tRCD = 18,
218 .tRCD = 18,
241 .tRCD = 18,
263 .tRCD = 3,
/rk3399_rockchip-uboot/arch/arm/mach-omap2/omap5/
H A Demif.c29 .tRCD = 18,
58 .tRCD = 3,
H A Dsdram.c613 .tRCD = 18,
635 .tRCD = 3,
/rk3399_rockchip-uboot/arch/arm/mach-sunxi/
H A Ddram_sun9i.c129 u32 tRCD; /* in ps */ member
380 const u32 tRCD = PS2CYCLES_ROUNDUP(para->tRCD); in mctl_channel_init() local
551 writel((MCTL_DIV2(tRCD) << 24) | (MCTL_DIV2(tCCD) << 16) | in mctl_channel_init()
645 (tRCD << 12) | (tRP << 8) | (tWTR << 4) | (tRTP << 0), in mctl_channel_init()
891 .tRCD = 13750, in sunxi_dram_init()
/rk3399_rockchip-uboot/arch/arm/include/asm/
H A Demif.h1098 u8 tRCD; member
1127 u32 tRCD; member
/rk3399_rockchip-uboot/doc/device-tree-bindings/clock/
H A Drockchip,rk3288-dmc.txt50 rockchip,trcd: tRCD,AC timing parameters from the memory data-sheet
/rk3399_rockchip-uboot/board/buffalo/lsxl/
H A Dkwbimage-lschl.cfg58 # bit7-4: 4, 5 cycle tRCD
H A Dkwbimage-lsxhl.cfg58 # bit7-4: 4, 5 cycle tRCD
/rk3399_rockchip-uboot/board/d-link/dns325/
H A Dkwbimage.cfg55 # bit7-4: 5, 6 cycle tRCD
/rk3399_rockchip-uboot/arch/arm/mach-omap2/
H A Demif-common.c621 val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1; in get_sdram_tim_1_reg()