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Searched refs:spin (Results 1 – 8 of 8) sorted by relevance

/rk3399_rockchip-uboot/doc/
H A DREADME.mpc85xx-spin-table3 As specified by ePAPR v1.1, the spin table needs to be in cached memory. After
4 DDR is initialized and U-Boot relocates itself into DDR, the spin table is
6 __secondary_start_page. For other cores to use the spin table, the booting
15 core 0 puts the physical address of the spin table (which is in release.S and
21 the new space. The new TLB covers the physical address of the spin table page,
22 with WIMGE =0b00100. Now secondary cores can keep polling the spin table
23 without stress DDR bus because both the code and the spin table is in cache.
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dbcm2837.dtsi38 enable-method = "spin-table";
46 enable-method = "spin-table";
54 enable-method = "spin-table";
62 enable-method = "spin-table";
/rk3399_rockchip-uboot/arch/arm/cpu/armv8/
H A DKconfig25 bool "Support spin-table enable method"
28 Say Y here to support "spin-table" enable method for booting Linux.
31 - Specify enable-method = "spin-table" in each CPU node in the
35 secondary CPUs will spin in unprotected memory area because the
36 master CPU protects the relocated spin code.
41 - Reserve the code for the spin-table and the release address
/rk3399_rockchip-uboot/board/freescale/common/
H A DKconfig20 esbc_halt - put the core in spin loop (Secure Boot Only)
/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc85xx/
H A Dcpu_init.c732 const char *spin; in cpu_init_r() local
797 spin = env_get("spin_table_compat"); in cpu_init_r()
798 if (spin && (*spin == 'n')) in cpu_init_r()
H A DKconfig1191 in spin table to properly handle all cores.
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/ls102xa/
H A DKconfig44 in spin table to properly handle all cores.
/rk3399_rockchip-uboot/arch/arm/cpu/armv8/fsl-layerscape/
H A DKconfig239 in spin table to properly handle all cores.