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Searched refs:sclk (Results 1 – 25 of 38) sorted by relevance

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/rk3399_rockchip-uboot/arch/arm/mach-exynos/
H A Dclock.c368 unsigned long sclk = 0; in exynos5_get_periph_rate() local
438 sclk = exynos5_get_pll_clk(MPLL); in exynos5_get_periph_rate()
441 sclk = exynos5_get_pll_clk(EPLL); in exynos5_get_periph_rate()
444 sclk = exynos5_get_pll_clk(VPLL); in exynos5_get_periph_rate()
461 return (sclk / (div + 1)) / (sub_div + 1); in exynos5_get_periph_rate()
467 unsigned long sclk = 0; in exynos542x_get_periph_rate() local
529 sclk = exynos542x_get_pll_clk(MPLL); in exynos542x_get_periph_rate()
532 sclk = exynos542x_get_pll_clk(SPLL); in exynos542x_get_periph_rate()
535 sclk = exynos542x_get_pll_clk(EPLL); in exynos542x_get_periph_rate()
538 sclk = exynos542x_get_pll_clk(RPLL); in exynos542x_get_periph_rate()
[all …]
/rk3399_rockchip-uboot/board/freescale/common/
H A Dngpixis.c143 PIXIS_READ(sclk[0]), PIXIS_READ(sclk[1]), PIXIS_READ(sclk[2])); in pixis_dump_regs()
170 PIXIS_WRITE(sclk[0], sclk0); in pixis_sysclk_set()
171 PIXIS_WRITE(sclk[1], sclk1); in pixis_sysclk_set()
172 PIXIS_WRITE(sclk[2], sclk2); in pixis_sysclk_set()
H A Dics307_clk.c135 in_8(&fpga_reg->sclk[0]), in get_board_sys_clk()
136 in_8(&fpga_reg->sclk[1]), in get_board_sys_clk()
137 in_8(&fpga_reg->sclk[2])); in get_board_sys_clk()
H A Dpixis.h34 u8 sclk[3]; member
97 u8 sclk[3]; member
129 u8 sclk[3]; member
H A Dqixis.c183 printf("sclk = %02x%02x%02x\n", QIXIS_READ(sclk[0]), in qixis_dump_regs()
184 QIXIS_READ(sclk[1]), QIXIS_READ(sclk[2])); in qixis_dump_regs()
H A Dngpixis.h39 u8 sclk[3]; member
H A Dqixis.h47 u8 sclk[3]; /* Clock Configuration Registers,0x34 */ member
/rk3399_rockchip-uboot/drivers/spi/
H A Dsoft_spi.c25 struct gpio_desc sclk; member
44 dm_gpio_set_value(&plat->sclk, bit); in soft_spi_scl()
65 dm_gpio_set_value(&plat->sclk, 0); in soft_spi_cs_activate()
226 (gpio_request_by_name(dev, "gpio-sck", 0, &plat->sclk, GPIOD_IS_OUT | clk_flags) && in soft_spi_probe()
227 gpio_request_by_name(dev, "sck-gpios", 0, &plat->sclk, GPIOD_IS_OUT | clk_flags))) in soft_spi_probe()
/rk3399_rockchip-uboot/drivers/mmc/
H A Dexynos_dw_mmc.c57 unsigned long sclk; in exynos_dwmci_get_clk() local
68 sclk = get_mmc_clk(host->dev_index); in exynos_dwmci_get_clk()
74 return sclk / clk_div / (host->div + 1); in exynos_dwmci_get_clk()
99 unsigned long freq, sclk; in exynos_dwmci_core_init() local
107 sclk = get_mmc_clk(host->dev_index); in exynos_dwmci_core_init()
108 div = DIV_ROUND_UP(sclk, freq); in exynos_dwmci_core_init()
H A Dftsdc010_mci.c27 uint32_t sclk; /* FTSDC010 source clock in Hz */ member
110 if (rate >= chip->sclk / (2 * (div + 1))) in ftsdc010_clkset()
113 chip->rate = chip->sclk / (2 * (div + 1)); in ftsdc010_clkset()
342 chip->sclk = CONFIG_SYS_CLK_FREQ; in ftsdc010_mmc_init()
344 chip->sclk = clk_get_rate("SDC"); in ftsdc010_mmc_init()
362 chip->cfg.f_max = chip->sclk / 2; in ftsdc010_mmc_init()
363 chip->cfg.f_min = chip->sclk / 0x100; in ftsdc010_mmc_init()
H A Ddw_mmc.c637 unsigned long sclk; local
647 sclk = host->get_mmc_clk(host, freq);
649 sclk = host->bus_hz;
655 if (sclk == 0)
658 if (sclk == freq)
661 div = DIV_ROUND_UP(sclk, 2 * freq);
/rk3399_rockchip-uboot/arch/arm/dts/
H A Drv1126-pinctrl.dtsi399 i2s0m0_sclk_rx: i2s0m0-sclk-rx {
403 i2s0m0_sclk_tx: i2s0m0-sclk-tx {
439 i2s0m1_sclk_rx: i2s0m1-sclk-rx {
443 i2s0m1_sclk_tx: i2s0m1-sclk-tx {
477 i2s1m0_sclk: i2s1m0-sclk {
497 i2s1m1_sclk: i2s1m1-sclk {
517 i2s1m2_sclk: i2s1m2-sclk {
539 i2s2m0_sclk: i2s2m0-sclk {
559 i2s2m1_sclk: i2s2m1-sclk {
H A Drk3562-pinctrl.dtsi335 i2s0m0_sclk: i2s0m0-sclk {
401 i2s0m1_sclk: i2s0m1-sclk {
469 i2s1m0_sclk: i2s1m0-sclk {
535 i2s1m1_sclk: i2s1m1-sclk {
603 i2s2m0_sclk: i2s2m0-sclk {
633 i2s2m1_sclk: i2s2m1-sclk {
H A Drk3576-pinctrl.dtsi2711 sai0m0_sclk: sai0m0-sclk {
2777 sai0m1_sclk: sai0m1-sclk {
2843 sai0m2_sclk: sai0m2-sclk {
2911 sai1m0_sclk: sai1m0-sclk {
2977 sai1m1_sclk: sai1m1-sclk {
3045 sai2m0_sclk: sai2m0-sclk {
3074 sai2m1_sclk: sai2m1-sclk {
3103 sai2m2_sclk: sai2m2-sclk {
3134 sai3m0_sclk: sai3m0-sclk {
3163 sai3m1_sclk: sai3m1-sclk {
[all …]
H A Drk3506-pinctrl-rmio.dtsi216 rm_io0_sai0_sclk: rm-io0-sai0-sclk {
248 rm_io0_sai1_sclk: rm-io0-sai1-sclk {
611 rm_io1_sai0_sclk: rm-io1-sai0-sclk {
643 rm_io1_sai1_sclk: rm-io1-sai1-sclk {
1006 rm_io2_sai0_sclk: rm-io2-sai0-sclk {
1038 rm_io2_sai1_sclk: rm-io2-sai1-sclk {
1401 rm_io3_sai0_sclk: rm-io3-sai0-sclk {
1433 rm_io3_sai1_sclk: rm-io3-sai1-sclk {
1796 rm_io4_sai0_sclk: rm-io4-sai0-sclk {
1828 rm_io4_sai1_sclk: rm-io4-sai1-sclk {
[all …]
H A Drk3506-pinctrl.dtsi868 sai0_sclk_pins: sai0-sclk-pins {
918 sai1_sclk_pins: sai1-sclk-pins {
968 sai2m0_sclk_pins: sai2m0-sclk-pins {
997 sai2m1_sclk_pins: sai2m1-sclk-pins {
1028 sai3_sclk_pins: sai3-sclk-pins {
H A Dsun5i-a13.dtsi198 clock-output-names = "tcon-ch0-sclk";
206 clock-output-names = "tcon-ch1-sclk";
H A Drv1126b-pinctrl.dtsi1258 sai0m0_sclk_pins: sai0m0-sclk-pins {
1324 sai0m1_sclk_pins: sai0m1-sclk-pins {
1392 sai1m0_sclk_pins: sai1m0-sclk-pins {
1421 sai1m1_sclk_pins: sai1m1-sclk-pins {
1450 sai1m2_sclk_pins: sai1m2-sclk-pins {
1481 sai2m0_sclk_pins: sai2m0-sclk-pins {
1523 sai2m1_sclk_pins: sai2m1-sclk-pins {
H A Drk3588-vccio3-pinctrl.dtsi241 i2s2m0_sclk: i2s2m0-sclk {
H A Drk3588s-pinctrl.dtsi907 i2s0_sclk: i2s0-sclk {
975 i2s1m0_sclk: i2s1m0-sclk {
1040 i2s1m1_sclk: i2s1m1-sclk {
1108 i2s2m1_sclk: i2s2m1-sclk {
1140 i2s3_sclk: i2s3-sclk {
H A Dsun4i-a10.dtsi624 clock-output-names = "tcon0-ch0-sclk";
634 clock-output-names = "tcon1-ch0-sclk";
643 clock-output-names = "tcon0-ch1-sclk";
652 clock-output-names = "tcon1-ch1-sclk";
H A Dstih407-pinctrl.dtsi1138 sclk = <&pio33 6 ALT1 OUT>;
1150 sclk = <&pio33 6 ALT1 OUT>;
1161 sclk = <&pio32 6 ALT1 IN>;
1174 sclk = <&pio32 6 ALT1 IN>;
/rk3399_rockchip-uboot/doc/device-tree-bindings/spi/
H A Dsoft-spi.txt26 sclk-gpio = <&gpio 225 0>; /* Y31 */
/rk3399_rockchip-uboot/doc/device-tree-bindings/clock/
H A Dnvidia,tegra20-car.txt138 107 sclk
/rk3399_rockchip-uboot/doc/device-tree-bindings/video/
H A Dexynos-fb.txt56 samsung,sclk-div: parent_clock/source_clock ratio

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