1*623b6386SSimon GlassSoft SPI 2*623b6386SSimon Glass 3*623b6386SSimon GlassThe soft SPI bus implementation allows the use of GPIO pins to simulate a 4*623b6386SSimon GlassSPI bus. No SPI host is required for this to work. The down-side is that the 5*623b6386SSimon Glassperformance will typically be much lower than a real SPI bus. 6*623b6386SSimon Glass 7*623b6386SSimon GlassThe soft SPI node requires the following properties: 8*623b6386SSimon Glass 9*623b6386SSimon Glasscompatible: "u-boot,soft-spi" 10*623b6386SSimon Glasssoft_spi_cs: GPIO number to use for SPI chip select (output) 11*623b6386SSimon Glasssoft_spi_sclk: GPIO number to use for SPI clock (output) 12*623b6386SSimon Glasssoft_spi_mosi: GPIO number to use for SPI MOSI line (output) 13*623b6386SSimon Glasssoft_spi_miso GPIO number to use for SPI MISO line (input) 14*623b6386SSimon Glassspi-delay-us: Number of microseconds of delay between each CS transition 15*623b6386SSimon Glass 16*623b6386SSimon GlassThe GPIOs should be specified as required by the GPIO controller referenced. 17*623b6386SSimon GlassThe first cell holds the phandle of the controller and the second cell 18*623b6386SSimon Glasstypically holds the GPIO number. 19*623b6386SSimon Glass 20*623b6386SSimon Glass 21*623b6386SSimon GlassExample: 22*623b6386SSimon Glass 23*623b6386SSimon Glass soft-spi { 24*623b6386SSimon Glass compatible = "u-boot,soft-spi"; 25*623b6386SSimon Glass cs-gpio = <&gpio 235 0>; /* Y43 */ 26*623b6386SSimon Glass sclk-gpio = <&gpio 225 0>; /* Y31 */ 27*623b6386SSimon Glass mosi-gpio = <&gpio 227 0>; /* Y33 */ 28*623b6386SSimon Glass miso-gpio = <&gpio 224 0>; /* Y30 */ 29*623b6386SSimon Glass spi-delay-us = <1>; 30*623b6386SSimon Glass #address-cells = <1>; 31*623b6386SSimon Glass #size-cells = <0>; 32*623b6386SSimon Glass cs@0 { 33*623b6386SSimon Glass }; 34*623b6386SSimon Glass }; 35