xref: /rk3399_rockchip-uboot/arch/arm/dts/sun5i-a13.dtsi (revision c6b968da78ce3fa7224c0ddf15fe170c7c05b27e)

/*
 * Copyright 2012 Maxime Ripard
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This library is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This library is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include "skeleton.dtsi"

#include "sun5i.dtsi"

#include <dt-bindings/pinctrl/sun4i-a10.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	interrupt-parent = <&intc>;

	chosen {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		framebuffer@0 {
			compatible = "allwinner,simple-framebuffer",
				     "simple-framebuffer";
			allwinner,pipeline = "de_be0-lcd0";
			clocks = <&ahb_gates 36>, <&ahb_gates 44>, <&de_be_clk>,
				 <&tcon_ch0_clk>, <&dram_gates 26>;
			status = "disabled";
		};
	};

	thermal-zones {
		cpu_thermal {
			/* milliseconds */
			polling-delay-passive = <250>;
			polling-delay = <1000>;
			thermal-sensors = <&rtp>;

			cooling-maps {
				map0 {
					trip = <&cpu_alert0>;
					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};

			trips {
				cpu_alert0: cpu_alert0 {
					/* milliCelsius */
					temperature = <850000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu_crit: cpu_crit {
					/* milliCelsius */
					temperature = <100000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};
	};

	clocks {
		ahb_gates: clk@01c20060 {
			#clock-cells = <1>;
			compatible = "allwinner,sun5i-a13-ahb-gates-clk";
			reg = <0x01c20060 0x8>;
			clocks = <&ahb>;
			clock-indices = <0>, <1>,
					<2>, <5>, <6>,
					<7>, <8>, <9>,
					<10>, <13>,
					<14>, <20>,
					<21>, <22>,
					<28>, <32>, <34>,
					<36>, <40>, <44>,
					<46>, <51>,
					<52>;
			clock-output-names = "ahb_usbotg", "ahb_ehci",
					     "ahb_ohci", "ahb_ss", "ahb_dma",
					     "ahb_bist", "ahb_mmc0", "ahb_mmc1",
					     "ahb_mmc2", "ahb_nand",
					     "ahb_sdram", "ahb_spi0",
					     "ahb_spi1", "ahb_spi2",
					     "ahb_stimer", "ahb_ve", "ahb_tve",
					     "ahb_lcd", "ahb_csi", "ahb_de_be",
					     "ahb_de_fe", "ahb_iep",
					     "ahb_mali400";
		};

		apb0_gates: clk@01c20068 {
			#clock-cells = <1>;
			compatible = "allwinner,sun5i-a13-apb0-gates-clk";
			reg = <0x01c20068 0x4>;
			clocks = <&apb0>;
			clock-indices = <0>, <5>,
					<6>;
			clock-output-names = "apb0_codec", "apb0_pio",
					     "apb0_ir";
		};

		apb1_gates: clk@01c2006c {
			#clock-cells = <1>;
			compatible = "allwinner,sun5i-a13-apb1-gates-clk";
			reg = <0x01c2006c 0x4>;
			clocks = <&apb1>;
			clock-indices = <0>, <1>,
					<2>, <17>,
					<19>;
			clock-output-names = "apb1_i2c0", "apb1_i2c1",
					     "apb1_i2c2", "apb1_uart1",
					     "apb1_uart3";
		};

		dram_gates: clk@01c20100 {
			#clock-cells = <1>;
			compatible = "allwinner,sun5i-a13-dram-gates-clk",
				     "allwinner,sun4i-a10-gates-clk";
			reg = <0x01c20100 0x4>;
			clocks = <&pll5 0>;
			clock-indices = <0>,
					<1>,
					<25>,
					<26>,
					<29>,
					<31>;
			clock-output-names = "dram_ve",
					     "dram_csi",
					     "dram_de_fe",
					     "dram_de_be",
					     "dram_ace",
					     "dram_iep";
		};

		de_be_clk: clk@01c20104 {
			#clock-cells = <0>;
			#reset-cells = <0>;
			compatible = "allwinner,sun4i-a10-display-clk";
			reg = <0x01c20104 0x4>;
			clocks = <&pll3>, <&pll7>, <&pll5 1>;
			clock-output-names = "de-be";
		};

		de_fe_clk: clk@01c2010c {
			#clock-cells = <0>;
			#reset-cells = <0>;
			compatible = "allwinner,sun4i-a10-display-clk";
			reg = <0x01c2010c 0x4>;
			clocks = <&pll3>, <&pll7>, <&pll5 1>;
			clock-output-names = "de-fe";
		};

		tcon_ch0_clk: clk@01c20118 {
			#clock-cells = <0>;
			#reset-cells = <1>;
			compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
			reg = <0x01c20118 0x4>;
			clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
			clock-output-names = "tcon-ch0-sclk";
		};

		tcon_ch1_clk: clk@01c2012c {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
			reg = <0x01c2012c 0x4>;
			clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
			clock-output-names = "tcon-ch1-sclk";
		};
	};

	display-engine {
		compatible = "allwinner,sun5i-a13-display-engine";
		allwinner,pipelines = <&fe0>;
	};

	soc@01c00000 {
		tcon0: lcd-controller@01c0c000 {
			compatible = "allwinner,sun5i-a13-tcon";
			reg = <0x01c0c000 0x1000>;
			interrupts = <44>;
			resets = <&tcon_ch0_clk 1>;
			reset-names = "lcd";
			clocks = <&ahb_gates 36>,
				 <&tcon_ch0_clk>,
				 <&tcon_ch1_clk>;
			clock-names = "ahb",
				      "tcon-ch0",
				      "tcon-ch1";
			clock-output-names = "tcon-pixel-clock";
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				tcon0_in: port@0 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0>;

					tcon0_in_be0: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&be0_out_tcon0>;
					};
				};

				tcon0_out: port@1 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <1>;
				};
			};
		};

		pwm: pwm@01c20e00 {
			compatible = "allwinner,sun5i-a13-pwm";
			reg = <0x01c20e00 0xc>;
			clocks = <&osc24M>;
			#pwm-cells = <3>;
			status = "disabled";
		};

		fe0: display-frontend@01e00000 {
			compatible = "allwinner,sun5i-a13-display-frontend";
			reg = <0x01e00000 0x20000>;
			interrupts = <47>;
			clocks = <&ahb_gates 46>, <&de_fe_clk>,
				 <&dram_gates 25>;
			clock-names = "ahb", "mod",
				      "ram";
			resets = <&de_fe_clk>;
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				fe0_out: port@1 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <1>;

					fe0_out_be0: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&be0_in_fe0>;
					};
				};
			};
		};

		be0: display-backend@01e60000 {
			compatible = "allwinner,sun5i-a13-display-backend";
			reg = <0x01e60000 0x10000>;
			clocks = <&ahb_gates 44>, <&de_be_clk>,
				 <&dram_gates 26>;
			clock-names = "ahb", "mod",
				      "ram";
			resets = <&de_be_clk>;
			status = "disabled";

			assigned-clocks = <&de_be_clk>;
			assigned-clock-rates = <300000000>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				be0_in: port@0 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0>;

					be0_in_fe0: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&fe0_out_be0>;
					};
				};

				be0_out: port@1 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <1>;

					be0_out_tcon0: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&tcon0_in_be0>;
					};
				};
			};
		};
	};
};

&cpu0 {
	clock-latency = <244144>; /* 8 32k periods */
	operating-points = <
		/* kHz	  uV */
		1008000 1400000
		912000	1350000
		864000	1300000
		624000	1200000
		576000	1200000
		432000	1200000
		>;
	#cooling-cells = <2>;
	cooling-min-level = <0>;
	cooling-max-level = <5>;
};

&pio {
	compatible = "allwinner,sun5i-a13-pinctrl";

	lcd_rgb666_pins: lcd_rgb666@0 {
		allwinner,pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
				 "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
				 "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
				 "PD24", "PD25", "PD26", "PD27";
		allwinner,function = "lcd0";
		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
	};

	uart1_pins_a: uart1@0 {
		allwinner,pins = "PE10", "PE11";
		allwinner,function = "uart1";
		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
	};

	uart1_pins_b: uart1@1 {
		allwinner,pins = "PG3", "PG4";
		allwinner,function = "uart1";
		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
	};
};