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/rk3399_rockchip-uboot/doc/device-tree-bindings/reset/
H A Dreset.txt3 This binding is intended to represent the hardware reset signals present
8 Hardware blocks typically receive a reset signal. This signal is generated by
9 a reset provider (e.g. power management or clock module) and received by a
10 reset consumer (the module being reset, or a module managing when a sub-
11 ordinate module is reset). This binding exists to represent the provider and
14 A reset signal is represented by the phandle of the provider, plus a reset
15 specifier - a list of DT cells that represents the reset signal within the
16 provider. The length (number of cells) and semantics of the reset specifier
17 are dictated by the binding of the reset provider, although common schemes
20 A word on where to place reset signal consumers in device tree: It is possible
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/rk3399_rockchip-uboot/drivers/reset/
H A DKconfig4 bool "Enable reset controllers using Driver Model"
7 Enable support for the reset controller driver class. Many hardware
8 modules are equipped with a reset signal, typically driven by some
9 reset controller hardware module within the chip. In U-Boot, reset
10 controller drivers allow control over these reset signals. In some
12 although driving such reset isgnals using GPIOs may be more
16 bool "Enable reset controllers using Driver Model in SPL"
19 Enable support for the reset controller driver class. Many hardware
20 modules are equipped with a reset signal, typically driven by some
21 reset controller hardware module within the chip. In U-Boot, reset
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H A DMakefile5 obj-$(CONFIG_$(SPL_)DM_RESET) += reset-uclass.o
6 obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset.o
7 obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o
8 obj-$(CONFIG_STI_RESET) += sti-reset.o
9 obj-$(CONFIG_TEGRA_CAR_RESET) += tegra-car-reset.o
10 obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
11 obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
12 obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
13 obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o
14 obj-$(CONFIG_$(SPL_)RESET_ROCKCHIP) += reset-rockchip.o
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/rk3399_rockchip-uboot/drivers/sysreset/
H A DKconfig2 # System reset devices
5 menu "System reset device drivers"
8 bool "Enable support for system reset drivers"
11 Enable system reset drivers which can be used to reset the CPU or
12 board. Each driver can provide a reset method which will be called
13 to effect a reset. The uclass will try all available drivers when
17 bool "Enable support for system reset drivers in SPL mode"
20 Enable system reset drivers which can be used to reset the CPU or
21 board. Each driver can provide a reset method which will be called
22 to effect a reset. The uclass will try all available drivers when
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/rk3399_rockchip-uboot/doc/device-tree-bindings/exynos/
H A Demmc-reset.txt1 * Samsung eMMC reset
7 - compatible: should be "samsung,emmc-reset"
8 - reset-gpio: gpio chip for eMMC reset.
12 emmc-reset {
13 compatible = "samsung,emmc-reset";
14 reset-gpio = <&gpk1 2 0>;
/rk3399_rockchip-uboot/doc/device-tree-bindings/gpu/
H A Dnvidia,tegra20-host1x.txt14 - resets: Must contain an entry for each entry in reset-names.
15 See ../reset/reset.txt for details.
16 - reset-names: Must include the following entries:
30 - resets: Must contain an entry for each entry in reset-names.
31 See ../reset/reset.txt for details.
32 - reset-names: Must include the following entries:
43 - resets: Must contain an entry for each entry in reset-names.
44 See ../reset/reset.txt for details.
45 - reset-names: Must include the following entries:
56 - resets: Must contain an entry for each entry in reset-names.
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/rk3399_rockchip-uboot/arch/arm/mach-omap2/omap3/
H A Demac.c21 u32 reset; in cpu_eth_init() local
24 reset = readl(&am35x_scm_general_regs->ip_sw_reset); in cpu_eth_init()
25 reset &= ~CPGMACSS_SW_RST; in cpu_eth_init()
26 writel(reset, &am35x_scm_general_regs->ip_sw_reset); in cpu_eth_init()
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dast2500-u-boot.dtsi2 #include <dt-bindings/reset/ast2500-reset.h>
12 #reset-cells = <1>;
15 rst: reset-controller {
17 compatible = "aspeed,ast2500-reset";
19 #reset-cells = <1>;
27 #reset-cells = <1>;
H A Dtegra30.dtsi47 reset-names = "pex", "afi", "pcie_x";
97 reset-names = "host1x";
110 reset-names = "mpe";
119 reset-names = "vi";
128 reset-names = "epp";
137 reset-names = "isp";
146 reset-names = "2d";
157 reset-names = "3d", "3d2";
168 reset-names = "dc";
187 reset-names = "dc";
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H A Dtegra20.dtsi19 reset-names = "host1x";
32 reset-names = "mpe";
41 reset-names = "vi";
50 reset-names = "epp";
59 reset-names = "isp";
68 reset-names = "2d";
76 reset-names = "3d";
87 reset-names = "dc";
104 reset-names = "dc";
121 reset-names = "hdmi";
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H A Dtegra114.dtsi20 reset-names = "host1x";
33 reset-names = "2d";
41 reset-names = "3d";
52 reset-names = "dc";
71 reset-names = "dc";
90 reset-names = "hdmi";
102 reset-names = "dsi";
118 reset-names = "dsi";
168 #reset-cells = <1>;
213 reset-names = "dma";
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H A Dtegra124.dtsi7 #include <dt-bindings/reset/tegra124-car.h>
50 reset-names = "pex", "afi", "pcie_x";
90 reset-names = "host1x";
105 reset-names = "dc";
120 reset-names = "dc";
135 reset-names = "hdmi";
149 reset-names = "sor";
161 reset-names = "dpaux";
190 reset-names = "gpu";
225 #reset-cells = <1>;
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H A Dtegra210.dtsi47 reset-names = "pex", "afi", "pcie_x";
88 reset-names = "host1x";
103 reset-names = "dpaux";
127 reset-names = "dc";
142 reset-names = "dc";
157 reset-names = "dsi";
186 reset-names = "dsi";
223 reset-names = "sor";
237 reset-names = "sor";
249 reset-names = "dpaux";
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H A Drk3568-evb.dts37 snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
38 snps,reset-active-low;
40 snps,reset-delays-us = <0 20000 100000>;
63 snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
64 snps,reset-active-low;
66 snps,reset-delays-us = <0 20000 100000>;
/rk3399_rockchip-uboot/doc/device-tree-bindings/net/
H A Dstmmac.txt14 - snps,reset-gpio gpio number for phy reset.
15 - snps,reset-active-low boolean flag to indicate if phy reset is active low.
16 - snps,reset-delays-us is triplet of delays
17 The 1st cell is reset pre-delay in micro seconds.
18 The 2nd cell is reset pulse in micro seconds.
19 The 3rd cell is reset post-delay in micro seconds.
34 - resets: Should contain a phandle to the STMMAC reset signal, if any
35 - reset-names: Should contain the reset signal name "stmmaceth", if a
36 reset phandle is given
/rk3399_rockchip-uboot/arch/arm/cpu/armv7m/
H A Dstart.S10 .globl reset symbol
11 .type reset, %function
12 reset: label
/rk3399_rockchip-uboot/board/logicpd/am3517evm/
H A Dam3517evm.c64 .reset = am35x_musb_reset,
106 u32 reset; in misc_init_r() local
137 reset = readl(AM3517_IP_SW_RESET); in misc_init_r()
138 reset &= (~CPGMACSS_SW_RST); in misc_init_r()
139 writel(reset,AM3517_IP_SW_RESET); in misc_init_r()
/rk3399_rockchip-uboot/board/freescale/mpc8610hpcd/
H A DREADME39 A new command, "pixis_reset", is introduced to reset mpc8610hpcd board
55 /* reset to current bank, like "reset" command */
58 /* reset board but use the to alternate flash bank */
61 /* reset board, use alternate flash bank with watchdog timer enabled*/
64 /* reset board to alternate bank with frequency changed.
67 pixis-reset altbank cf 40 2.5 10
/rk3399_rockchip-uboot/arch/mips/dts/
H A Dbrcm,bcm3380.dtsi9 #include <dt-bindings/reset/bcm3380-reset.h>
74 periph_rst0: reset-controller@14e0008c {
75 compatible = "brcm,bcm6345-reset";
77 #reset-cells = <1>;
80 periph_rst1: reset-controller@14e00090 {
81 compatible = "brcm,bcm6345-reset";
83 #reset-cells = <1>;
/rk3399_rockchip-uboot/board/logicpd/imx6/
H A Dimx6logic.c67 struct gpio_desc reset; in fixup_enet_clock() local
92 ret = dm_gpio_lookup_name("GPIO4_9", &reset); in fixup_enet_clock()
98 ret = dm_gpio_request(&reset, "eth0_reset"); in fixup_enet_clock()
105 dm_gpio_set_dir_flags(&reset, GPIOD_IS_OUT); in fixup_enet_clock()
106 dm_gpio_set_value(&reset, 0); in fixup_enet_clock()
108 dm_gpio_set_value(&reset, 1); in fixup_enet_clock()
/rk3399_rockchip-uboot/doc/device-tree-bindings/clock/
H A Dst,stm32-rcc.txt4 The RCC IP is both a reset and a clock controller.
7 Please also refer to reset.txt for common reset controller binding usage.
15 - #reset-cells: 1, see below
24 #reset-cells = <1>;
41 To simplify the usage and to share bit definition with the reset and clock
81 Device nodes should specify the reset channel required in their "resets"
82 property, containing a phandle to the reset device node and an index specifying
88 For example, for CRC reset:
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-sunxi/
H A Dboot0.h9 b reset
17 b reset
38 b reset
/rk3399_rockchip-uboot/arch/arm/mach-socfpga/
H A Dreset_manager_gen5.c22 void socfpga_per_reset(u32 reset, int set) in socfpga_per_reset() argument
25 u32 rstmgr_bank = RSTMGR_BANK(reset); in socfpga_per_reset()
49 setbits_le32(reg, 1 << RSTMGR_RESET(reset)); in socfpga_per_reset()
51 clrbits_le32(reg, 1 << RSTMGR_RESET(reset)); in socfpga_per_reset()
/rk3399_rockchip-uboot/net/
H A Dmdio-uclass.c63 if (mdio_get_ops(dev)->reset) in mdio_reset()
64 return mdio_get_ops(dev)->reset(dev); in mdio_reset()
76 pdata->mii_bus->reset = mdio_reset; in dm_mdio_post_probe()
88 if (ops->reset) in dm_mdio_pre_remove()
89 ops->reset(dev); in dm_mdio_pre_remove()
/rk3399_rockchip-uboot/board/freescale/mpc8544ds/
H A DREADME15 board, a runtime reset through the FPGA can also affect a swap
16 on the flash bank mappings for the next reset cycle.
36 and then reset with that new image temporarily, use this:
57 A new command, "pixis_reset", is introduced to reset mpc8641hpcn board
73 /* reset to current bank, like "reset" command */
76 /* reset board but use the to alternate flash bank */
79 /* reset board, use alternate flash bank with watchdog timer enabled*/
82 /* reset board to alternate bank with frequency changed.
85 pixis-reset altbank cf 40 2.5 10

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