1be7064f8SJoseph Chen/* 2be7064f8SJoseph Chen * SPDX-License-Identifier: GPL-2.0+ 3be7064f8SJoseph Chen * 4be7064f8SJoseph Chen * (C) Copyright 2020 Rockchip Electronics Co., Ltd 5be7064f8SJoseph Chen */ 6be7064f8SJoseph Chen 7be7064f8SJoseph Chen/dts-v1/; 8be7064f8SJoseph Chen#include "rk3568.dtsi" 9be7064f8SJoseph Chen#include "rk3568-u-boot.dtsi" 10be7064f8SJoseph Chen#include <dt-bindings/input/input.h> 11be7064f8SJoseph Chen 12be7064f8SJoseph Chen/ { 13be7064f8SJoseph Chen model = "Rockchip RK3568 Evaluation Board"; 14be7064f8SJoseph Chen compatible = "rockchip,rk3568-evb", "rockchip,rk3568"; 15be7064f8SJoseph Chen 16be7064f8SJoseph Chen adc-keys { 17be7064f8SJoseph Chen compatible = "adc-keys"; 18be7064f8SJoseph Chen io-channels = <&saradc 0>; 19be7064f8SJoseph Chen io-channel-names = "buttons"; 20be7064f8SJoseph Chen keyup-threshold-microvolt = <1800000>; 21be7064f8SJoseph Chen u-boot,dm-spl; 22be7064f8SJoseph Chen status = "okay"; 23be7064f8SJoseph Chen 24be7064f8SJoseph Chen volumeup-key { 25be7064f8SJoseph Chen u-boot,dm-spl; 26be7064f8SJoseph Chen linux,code = <KEY_VOLUMEUP>; 27be7064f8SJoseph Chen label = "volume up"; 28be7064f8SJoseph Chen press-threshold-microvolt = <9>; 29be7064f8SJoseph Chen }; 30be7064f8SJoseph Chen }; 31be7064f8SJoseph Chen}; 32be7064f8SJoseph Chen 33*34ddf661SDavid Wu&gmac0 { 34*34ddf661SDavid Wu phy-mode = "rgmii"; 35*34ddf661SDavid Wu clock_in_out = "output"; 36*34ddf661SDavid Wu 37*34ddf661SDavid Wu snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; 38*34ddf661SDavid Wu snps,reset-active-low; 39*34ddf661SDavid Wu /* Reset time is 20ms, 100ms for rtl8211f */ 40*34ddf661SDavid Wu snps,reset-delays-us = <0 20000 100000>; 41*34ddf661SDavid Wu assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; 42*34ddf661SDavid Wu assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; 43*34ddf661SDavid Wu assigned-clock-rates = <0>, <125000000>; 44*34ddf661SDavid Wu 45*34ddf661SDavid Wu pinctrl-names = "default"; 46*34ddf661SDavid Wu pinctrl-0 = <&gmac0_miim 47*34ddf661SDavid Wu &gmac0_tx_bus2 48*34ddf661SDavid Wu &gmac0_rx_bus2 49*34ddf661SDavid Wu &gmac0_rgmii_clk 50*34ddf661SDavid Wu &gmac0_rgmii_bus>; 51*34ddf661SDavid Wu 52*34ddf661SDavid Wu tx_delay = <0x3c>; 53*34ddf661SDavid Wu rx_delay = <0x2f>; 54*34ddf661SDavid Wu 55*34ddf661SDavid Wu phy-handle = <&rgmii_phy0>; 56*34ddf661SDavid Wu status = "disabled"; 57*34ddf661SDavid Wu}; 58*34ddf661SDavid Wu 59*34ddf661SDavid Wu&gmac1 { 60*34ddf661SDavid Wu phy-mode = "rgmii"; 61*34ddf661SDavid Wu clock_in_out = "output"; 62*34ddf661SDavid Wu 63*34ddf661SDavid Wu snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; 64*34ddf661SDavid Wu snps,reset-active-low; 65*34ddf661SDavid Wu /* Reset time is 20ms, 100ms for rtl8211f */ 66*34ddf661SDavid Wu snps,reset-delays-us = <0 20000 100000>; 67*34ddf661SDavid Wu 68*34ddf661SDavid Wu assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; 69*34ddf661SDavid Wu assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; 70*34ddf661SDavid Wu assigned-clock-rates = <0>, <125000000>; 71*34ddf661SDavid Wu 72*34ddf661SDavid Wu pinctrl-names = "default"; 73*34ddf661SDavid Wu pinctrl-0 = <&gmac1m1_miim 74*34ddf661SDavid Wu &gmac1m1_tx_bus2 75*34ddf661SDavid Wu &gmac1m1_rx_bus2 76*34ddf661SDavid Wu &gmac1m1_rgmii_clk 77*34ddf661SDavid Wu &gmac1m1_rgmii_bus>; 78*34ddf661SDavid Wu 79*34ddf661SDavid Wu tx_delay = <0x4f>; 80*34ddf661SDavid Wu rx_delay = <0x26>; 81*34ddf661SDavid Wu 82*34ddf661SDavid Wu phy-handle = <&rgmii_phy1>; 83*34ddf661SDavid Wu status = "disabled"; 84*34ddf661SDavid Wu}; 85*34ddf661SDavid Wu 86*34ddf661SDavid Wu&mdio0 { 87*34ddf661SDavid Wu rgmii_phy0: phy@0 { 88*34ddf661SDavid Wu compatible = "ethernet-phy-ieee802.3-c22"; 89*34ddf661SDavid Wu reg = <0x0>; 90*34ddf661SDavid Wu }; 91*34ddf661SDavid Wu}; 92*34ddf661SDavid Wu 93*34ddf661SDavid Wu&mdio1 { 94*34ddf661SDavid Wu rgmii_phy1: phy@0 { 95*34ddf661SDavid Wu compatible = "ethernet-phy-ieee802.3-c22"; 96*34ddf661SDavid Wu reg = <0x0>; 97*34ddf661SDavid Wu }; 98*34ddf661SDavid Wu}; 99*34ddf661SDavid Wu 10094d677daSLin Jinhan&crypto { 10194d677daSLin Jinhan status = "okay"; 10294d677daSLin Jinhan}; 10394d677daSLin Jinhan 104be7064f8SJoseph Chen&uart2 { 105be7064f8SJoseph Chen status = "okay"; 106be7064f8SJoseph Chen}; 107