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Searched refs:registers (Results 1 – 25 of 148) sorted by relevance

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/rk3399_rockchip-uboot/arch/arm/lib/
H A Dstacktrace.c72 uint32_t registers[16]; member
226 ulong vsp = state->registers[SP]; in unwind_exec_insn()
234 state->registers[SP] += ((insn & INSN_VSP_SIZE_MASK) << 2) + 4; in unwind_exec_insn()
237 state->registers[SP] -= ((insn & INSN_VSP_SIZE_MASK) << 2) + 4; in unwind_exec_insn()
258 if (!pop_vsp(&state->registers[reg], &vsp, in unwind_exec_insn()
273 state->registers[SP] = in unwind_exec_insn()
274 state->registers[insn & INSN_STD_DATA_MASK]; in unwind_exec_insn()
287 if (!pop_vsp(&state->registers[reg], &vsp, in unwind_exec_insn()
295 if (!pop_vsp(&state->registers[14], &vsp, kernel_stack, in unwind_exec_insn()
319 if (!pop_vsp(&state->registers[reg], &vsp, in unwind_exec_insn()
[all …]
H A Dvectors_m.S14 mov r0, sp @ pass auto-saved registers as argument
19 mov r0, sp @ pass auto-saved registers as argument
24 mov r0, sp @ pass auto-saved registers as argument
29 mov r0, sp @ pass auto-saved registers as argument
34 mov r0, sp @ pass auto-saved registers as argument
/rk3399_rockchip-uboot/doc/device-tree-bindings/mmc/
H A Dmsm_sdhci.txt5 - reg: Base address and length of registers:
6 - Host controller registers (SDHCI)
7 - SD Core registers
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dfsl-ls2080a.dtsi95 reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
96 0x00 0x03480000 0x0 0x80000 /* lut registers */
110 reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
111 0x00 0x03580000 0x0 0x80000 /* lut registers */
125 reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
126 0x00 0x03680000 0x0 0x80000 /* lut registers */
140 reg = <0x00 0x03700000 0x0 0x80000 /* dbi registers */
141 0x00 0x03780000 0x0 0x80000 /* lut registers */
H A Dfsl-ls1046a.dtsi243 reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
244 0x00 0x03480000 0x0 0x40000 /* lut registers */
245 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
259 reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
260 0x00 0x03580000 0x0 0x40000 /* lut registers */
261 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */
276 reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
277 0x00 0x03680000 0x0 0x40000 /* lut registers */
278 0x00 0x036c0000 0x0 0x40000 /* pf controls registers */
H A Darmada-xp-mv78460.dtsi119 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
120 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
121 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
122 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
123 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
124 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
125 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
126 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
127 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
128 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
H A Darmada-xp-mv78260.dtsi102 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
103 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
104 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
105 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
106 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
107 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
108 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
109 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
110 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
H A Dfsl-ls1043a.dtsi242 reg = <0x00 0x03400000 0x0 0x10000 /* dbi registers */
243 0x00 0x03410000 0x0 0x10000 /* lut registers */
257 reg = <0x00 0x03500000 0x0 0x10000 /* dbi registers */
258 0x00 0x03510000 0x0 0x10000 /* lut registers */
273 reg = <0x00 0x03600000 0x0 0x10000 /* dbi registers */
274 0x00 0x03610000 0x0 0x10000 /* lut registers */
H A Dfsl-ls1012a.dtsi124 reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
125 0x00 0x03480000 0x0 0x40000 /* lut registers */
126 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
H A Darmada-xp-mv78230.dtsi101 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
102 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
103 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
104 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
105 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
/rk3399_rockchip-uboot/arch/arm/mach-omap2/
H A Dlowlevel_init.S54 push {r4-r12, lr} @ save registers - ROM code may pollute
55 @ our registers
67 push {r4-r12, lr} @ save registers - ROM code may pollute
68 @ our registers
/rk3399_rockchip-uboot/doc/
H A DREADME.fsl-esdhc5 operating Qixis FPGA relevant registers. The STAT_PRES1 register has SDHC
18 ESDHC IP is in little-endian mode. Accessing ESDHC registers can be
21 ESDHC IP is in big-endian mode. Accessing ESDHC registers can be determined
H A DREADME.fsl_iim28 Read operations are implemented as read accesses to the shadow registers,
37 this operation, the shadow registers are reloaded by the hardware (not
39 these registers).
43 registers, as explained in 30.4.5.4.
H A DREADME.mxc_ocotp31 Read operations are implemented as read accesses to the shadow registers,
41 Following this operation, the shadow registers are not reloaded by the
46 registers, as explained by the first paragraph in 46.2.1.3.
/rk3399_rockchip-uboot/doc/device-tree-bindings/pci/
H A Darmada8k-pcie.txt8 - reg: base addresses and lengths of the pcie control and global control registers.
9 "ctrl" registers points to the global control registers, while the "config" space
10 points to the pcie configuration registers as mentioned in dw-pcie dt bindings in the link below.
/rk3399_rockchip-uboot/doc/device-tree-bindings/gpio/
H A Dnvidia,tegra186-gpio.txt12 major sets of registers exist:
14 a) Security registers, which allow configuration of allowed access to the GPIO
15 register set. These registers exist in a single contiguous block of physical
19 Access to this set of registers is not necessary in all circumstances. Code
20 that wishes to configure access to the GPIO registers needs access to these
21 registers to do so. Code which simply wishes to read or write GPIO data does not
22 need access to these registers.
24 b) GPIO registers, which allow manipulation of the GPIO signals. In some GPIO
25 controllers, these registers are exposed via multiple "physical aliases" in
37 implemented GPIOs within each port varies. GPIO registers within a controller
[all …]
/rk3399_rockchip-uboot/drivers/pinctrl/nxp/
H A DKconfig16 property and configure related registers.
30 property and configure related registers.
44 property and configure related registers.
58 registers.
/rk3399_rockchip-uboot/doc/mvebu/
H A Darmada-8k-memory.txt15 0xF0000000 0xF0FFFFFF AP Internal registers space
19 0xF2000000 0xF3FFFFFF CP-0 Internal (configuration) registers
22 0xF4000000 0xF5FFFFFF CP-1 Internal (configuration) registers
/rk3399_rockchip-uboot/doc/device-tree-bindings/spmi/
H A Dspmi-msm.txt9 2) SPMI write command (master) registers (PMIC_ARB_CORE_SW_DEC_CHANNELS)
10 3) SPMI read command (observer) registers (PMIC_ARB_CORE_REGISTERS_OBS)
/rk3399_rockchip-uboot/doc/device-tree-bindings/gpu/
H A Dnvidia,tegra20-host1x.txt5 - reg: Physical base address and length of the controller's registers.
26 - reg: Physical base address and length of the controller's registers.
39 - reg: Physical base address and length of the controller's registers.
52 - reg: Physical base address and length of the controller's registers.
65 - reg: Physical base address and length of the controller's registers.
78 - reg: Physical base address and length of the controller's registers.
91 - reg: Physical base address and length of the controller's registers.
109 - reg: Physical base address and length of the controller's registers.
137 - reg: Physical base address and length of the controller's registers.
163 - reg: Physical base address and length of the controller's registers.
[all …]
/rk3399_rockchip-uboot/doc/device-tree-bindings/clock/
H A Dnvidia,tegra20-car.txt11 - reg : Should contain CAR registers location and length
18 registers. These IDs often match those in the CAR's RST_DEVICES registers,
22 within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
/rk3399_rockchip-uboot/doc/device-tree-bindings/serial/
H A Dmxc-serial.txt5 - reg: start address and size of the registers
H A Dmsm-serial.txt5 - reg: start address and size of the registers
H A Dxilinx_uartlite.txt5 - reg: Should contain UART controller registers location and length.
/rk3399_rockchip-uboot/doc/device-tree-bindings/usb/
H A Dehci-msm.txt5 - reg: start address and size of the registers

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