1*983e3700STom Rini/* 2*983e3700STom Rini * Board specific setup info 3*983e3700STom Rini * 4*983e3700STom Rini * (C) Copyright 2010 5*983e3700STom Rini * Texas Instruments, <www.ti.com> 6*983e3700STom Rini * 7*983e3700STom Rini * Author : 8*983e3700STom Rini * Aneesh V <aneesh@ti.com> 9*983e3700STom Rini * 10*983e3700STom Rini * SPDX-License-Identifier: GPL-2.0+ 11*983e3700STom Rini */ 12*983e3700STom Rini 13*983e3700STom Rini#include <config.h> 14*983e3700STom Rini#include <asm/arch/omap.h> 15*983e3700STom Rini#include <asm/omap_common.h> 16*983e3700STom Rini#include <asm/arch/spl.h> 17*983e3700STom Rini#include <linux/linkage.h> 18*983e3700STom Rini 19*983e3700STom Rini.arch_extension sec 20*983e3700STom Rini 21*983e3700STom Rini#ifdef CONFIG_SPL 22*983e3700STom RiniENTRY(save_boot_params) 23*983e3700STom Rini ldr r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS 24*983e3700STom Rini str r0, [r1] 25*983e3700STom Rini b save_boot_params_ret 26*983e3700STom RiniENDPROC(save_boot_params) 27*983e3700STom Rini 28*983e3700STom Rini#if !defined(CONFIG_TI_SECURE_DEVICE) && defined(CONFIG_ARMV7_LPAE) 29*983e3700STom RiniENTRY(switch_to_hypervisor) 30*983e3700STom Rini 31*983e3700STom Rini/* 32*983e3700STom Rini * Switch to hypervisor mode 33*983e3700STom Rini */ 34*983e3700STom Rini adr r0, save_sp 35*983e3700STom Rini str sp, [r0] 36*983e3700STom Rini adr r1, restore_from_hyp 37*983e3700STom Rini ldr r0, =0x102 38*983e3700STom Rini b omap_smc1 39*983e3700STom Rinirestore_from_hyp: 40*983e3700STom Rini adr r0, save_sp 41*983e3700STom Rini ldr sp, [r0] 42*983e3700STom Rini MRC p15, 4, R0, c1, c0, 0 43*983e3700STom Rini ldr r1, =0X1004 @Set cache enable bits for hypervisor mode 44*983e3700STom Rini orr r0, r0, r1 45*983e3700STom Rini MCR p15, 4, R0, c1, c0, 0 46*983e3700STom Rini b switch_to_hypervisor_ret 47*983e3700STom Rinisave_sp: 48*983e3700STom Rini .word 0x0 49*983e3700STom RiniENDPROC(switch_to_hypervisor) 50*983e3700STom Rini#endif 51*983e3700STom Rini#endif 52*983e3700STom Rini 53*983e3700STom RiniENTRY(omap_smc1) 54*983e3700STom Rini push {r4-r12, lr} @ save registers - ROM code may pollute 55*983e3700STom Rini @ our registers 56*983e3700STom Rini mov r12, r0 @ Service 57*983e3700STom Rini mov r0, r1 @ Argument 58*983e3700STom Rini 59*983e3700STom Rini dsb 60*983e3700STom Rini dmb 61*983e3700STom Rini smc 0 @ SMC #0 to enter monitor mode 62*983e3700STom Rini @ call ROM Code API for the service requested 63*983e3700STom Rini pop {r4-r12, pc} 64*983e3700STom RiniENDPROC(omap_smc1) 65*983e3700STom Rini 66*983e3700STom RiniENTRY(omap_smc_sec) 67*983e3700STom Rini push {r4-r12, lr} @ save registers - ROM code may pollute 68*983e3700STom Rini @ our registers 69*983e3700STom Rini mov r6, #0xFF @ Indicate new Task call 70*983e3700STom Rini mov r12, #0x00 @ Secure Service ID in R12 71*983e3700STom Rini 72*983e3700STom Rini dsb 73*983e3700STom Rini dmb 74*983e3700STom Rini smc 0 @ SMC #0 to enter monitor mode 75*983e3700STom Rini 76*983e3700STom Rini b omap_smc_sec_end @ exit at end of the service execution 77*983e3700STom Rini nop 78*983e3700STom Rini 79*983e3700STom Rini @ In case of IRQ happening in Secure, then ARM will branch here. 80*983e3700STom Rini @ At that moment, IRQ will be pending and ARM will jump to Non Secure 81*983e3700STom Rini @ IRQ handler 82*983e3700STom Rini mov r12, #0xFE 83*983e3700STom Rini 84*983e3700STom Rini dsb 85*983e3700STom Rini dmb 86*983e3700STom Rini smc 0 @ SMC #0 to enter monitor mode 87*983e3700STom Rini 88*983e3700STom Riniomap_smc_sec_end: 89*983e3700STom Rini pop {r4-r12, pc} 90*983e3700STom RiniENDPROC(omap_smc_sec) 91