| /rk3399_rockchip-uboot/drivers/mtd/nand/raw/ |
| H A D | nand_ecc.c | 69 uint8_t idx, reg1, reg2, reg3, tmp1, tmp2; in nand_calculate_ecc() local
73 reg1 = reg2 = reg3 = 0; in nand_calculate_ecc()
84 reg2 ^= ~((uint8_t) i); in nand_calculate_ecc()
90 tmp1 |= (reg2 & 0x80) >> 1; /* B7 -> B6 */ in nand_calculate_ecc()
92 tmp1 |= (reg2 & 0x40) >> 2; /* B6 -> B4 */ in nand_calculate_ecc()
94 tmp1 |= (reg2 & 0x20) >> 3; /* B5 -> B2 */ in nand_calculate_ecc()
96 tmp1 |= (reg2 & 0x10) >> 4; /* B4 -> B0 */ in nand_calculate_ecc()
99 tmp2 |= (reg2 & 0x08) << 3; /* B3 -> B6 */ in nand_calculate_ecc()
101 tmp2 |= (reg2 & 0x04) << 2; /* B2 -> B4 */ in nand_calculate_ecc()
103 tmp2 |= (reg2 & 0x02) << 1; /* B1 -> B2 */ in nand_calculate_ecc()
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/ |
| H A D | sdram_common.h | 368 #define SYS_REG_DEC_ROW_3_4_V3(reg2, ch) SYS_REG_DEC_ROW_3_4(reg2, ch) argument
370 #define SYS_REG_DEC_CHINFO_V3(reg2, ch) SYS_REG_DEC_CHINFO(reg2, ch) argument
371 #define SYS_REG_ENC_DDRTYPE_V3(n, reg2, reg3) do { \ argument
372 (reg2) &= (~(0x7 << 13)); \
374 (reg2) |= (((n) & 0x7) << 13); \
377 #define SYS_REG_DEC_DDRTYPE_V3(reg2, reg3) \ argument
378 ((((reg2) >> 13) & 0x7) | \
382 #define SYS_REG_DEC_NUM_CH_V3(reg2) SYS_REG_DEC_NUM_CH(reg2) argument
384 #define SYS_REG_DEC_CH1_3_RANK(reg2) SYS_REG_DEC_RANK(reg2, 1) argument
385 #define SYS_REG_ENC_CH0_2_RANK_V3(n, reg2, reg3) do { \ argument
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| /rk3399_rockchip-uboot/post/lib_powerpc/ |
| H A D | threex.c | 128 unsigned int reg2 = (reg + 2) % 32; in cpu_post_test_threex() local
138 ASM_STW(reg2, stk, 0), in cpu_post_test_threex()
141 ASM_12X(test->cmd, reg2, reg1, reg0), in cpu_post_test_threex()
142 ASM_STW(reg2, stk, 12), in cpu_post_test_threex()
143 ASM_LWZ(reg2, stk, 0), in cpu_post_test_threex()
159 ASM_STW(reg2, stk, 0), in cpu_post_test_threex()
162 ASM_12X(test->cmd, reg2, reg1, reg0) | BIT_C, in cpu_post_test_threex()
163 ASM_STW(reg2, stk, 12), in cpu_post_test_threex()
164 ASM_LWZ(reg2, stk, 0), in cpu_post_test_threex()
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| H A D | rlwnm.c | 63 unsigned int reg2 = (reg + 2) % 32; in cpu_post_test_rlwnm() local
73 ASM_STW(reg2, stk, 0), in cpu_post_test_rlwnm()
76 ASM_122(test->cmd, reg2, reg1, reg0, test->mb, test->me), in cpu_post_test_rlwnm()
77 ASM_STW(reg2, stk, 12), in cpu_post_test_rlwnm()
78 ASM_LWZ(reg2, stk, 0), in cpu_post_test_rlwnm()
94 ASM_STW(reg2, stk, 0), in cpu_post_test_rlwnm()
97 ASM_122(test->cmd, reg2, reg1, reg0, test->mb, test->me) | in cpu_post_test_rlwnm()
99 ASM_STW(reg2, stk, 12), in cpu_post_test_rlwnm()
100 ASM_LWZ(reg2, stk, 0), in cpu_post_test_rlwnm()
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| H A D | three.c | 158 unsigned int reg2 = (reg + 2) % 32; in cpu_post_test_three() local
168 ASM_STW(reg2, stk, 0), in cpu_post_test_three()
171 ASM_12(test->cmd, reg2, reg1, reg0), in cpu_post_test_three()
172 ASM_STW(reg2, stk, 12), in cpu_post_test_three()
173 ASM_LWZ(reg2, stk, 0), in cpu_post_test_three()
189 ASM_STW(reg2, stk, 0), in cpu_post_test_three()
192 ASM_12(test->cmd, reg2, reg1, reg0) | BIT_C, in cpu_post_test_three()
193 ASM_STW(reg2, stk, 12), in cpu_post_test_three()
194 ASM_LWZ(reg2, stk, 0), in cpu_post_test_three()
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| /rk3399_rockchip-uboot/arch/arm/lib/ |
| H A D | memcpy.S | 23 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
24 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
27 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
28 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
39 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
40 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
47 .macro enter reg1 reg2 argument
48 stmdb sp!, {r0, \reg1, \reg2}
51 .macro exit reg1 reg2 argument
52 ldmfd sp!, {r0, \reg1, \reg2}
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| /rk3399_rockchip-uboot/include/ |
| H A D | ppc_asm.tmpl | 165 #define EXCEPTION_PROLOG(reg1, reg2) \
186 mfspr r23,reg2; \
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| /rk3399_rockchip-uboot/drivers/spi/ |
| H A D | fsl_qspi.c | 409 u32 reg, reg2; in qspi_enable_ddr_mode() local
417 reg2 = qspi_read32(priv->flags, ®s->smpr); in qspi_enable_ddr_mode()
418 reg2 &= ~QSPI_SMPR_DDRSMP_MASK; in qspi_enable_ddr_mode()
419 reg2 |= (2 << QSPI_SMPR_DDRSMP_SHIFT); in qspi_enable_ddr_mode()
420 qspi_write32(priv->flags, ®s->smpr, reg2); in qspi_enable_ddr_mode()
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