| /rk3399_rockchip-uboot/arch/arm/mach-davinci/include/mach/ |
| H A D | dm365_lowlevel.h | 17 int dm365_pll1_init(unsigned long pllmult, unsigned long prediv);
18 int dm365_pll2_init(unsigned long pllm, unsigned long prediv);
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| H A D | pll_defs.h | 20 unsigned int prediv; /* 0x114 */ member
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| H A D | hardware.h | 402 dv_reg prediv; member
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| /rk3399_rockchip-uboot/drivers/video/rockchip/ |
| H A D | rk_mipi.c | 204 u64 prediv = 1; in rk_mipi_phy_enable() local
277 prediv = i; in rk_mipi_phy_enable()
281 fbdiv = ddr_clk * prediv / refclk; in rk_mipi_phy_enable()
282 ddr_clk = refclk * fbdiv / prediv; in rk_mipi_phy_enable()
286 __func__, refclk, prediv, fbdiv, ddr_clk); in rk_mipi_phy_enable()
289 test_data[0] = prediv - 1; in rk_mipi_phy_enable()
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| /rk3399_rockchip-uboot/arch/arm/mach-davinci/ |
| H A D | dm365_lowlevel.c | 26 int dm365_pll1_init(unsigned long pllmult, unsigned long prediv) in dm365_pll1_init() argument
58 writel(prediv, &dv_pll0_regs->prediv); in dm365_pll1_init()
103 int dm365_pll2_init(unsigned long pllm, unsigned long prediv) in dm365_pll2_init() argument
140 writel(prediv, &dv_pll1_regs->prediv); in dm365_pll2_init()
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| H A D | da850_lowlevel.c | 86 ®->prediv); in da850_pll_init()
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| /rk3399_rockchip-uboot/drivers/video/drm/ |
| H A D | inno_video_combo_phy.c | 315 u8 prediv; member
409 REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv)); in inno_mipi_dphy_max_2_5GHz_pll_enable()
428 REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv)); in inno_mipi_dphy_max_1GHz_pll_enable()
665 u8 prediv = 2; in inno_video_phy_lvds_mode_enable() local
690 REG_PREDIV_MASK, REG_PREDIV(prediv)); in inno_video_phy_lvds_mode_enable()
802 u8 *prediv, u16 *fbdiv) in inno_video_phy_pll_round_rate() argument
862 *prediv = best_prediv; in inno_video_phy_pll_round_rate()
875 u8 prediv = 1; in inno_video_phy_set_pll() local
878 fout = inno_video_phy_pll_round_rate(fin, rate, &prediv, &fbdiv); in inno_video_phy_set_pll()
881 fin, fout, prediv, fbdiv); in inno_video_phy_set_pll()
[all …]
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| H A D | samsung_mipi_dcphy.c | 230 u8 prediv; member
1322 S(samsung->pll.scaler) | P(samsung->pll.prediv)); in samsung_mipi_dcphy_pll_configure()
1650 u16 prediv, u16 fbdiv, u8 *mfr, u8 *mrr) in samsung_mipi_dcphy_pll_ssc_modulation_calc() argument
1659 max_mfr = DIV_ROUND_UP(fin, (30 * prediv) << 5); in samsung_mipi_dcphy_pll_ssc_modulation_calc()
1660 min_mfr = div64_ul(fin, ((33 * prediv) << 5)); in samsung_mipi_dcphy_pll_ssc_modulation_calc()
1661 mid_mfr = div64_ul(fin, (31 * prediv) << 5); in samsung_mipi_dcphy_pll_ssc_modulation_calc()
1693 *mfr, *mrr, div64_ul(fin, (prediv * *mfr) << 5), in samsung_mipi_dcphy_pll_ssc_modulation_calc()
1707 u8 *prediv, u16 *fbdiv, u16 *dsm, u8 *scaler, u8 *mfr, u8 *mrr) in samsung_mipi_dcphy_pll_round_rate() argument
1807 *prediv = best_prediv; in samsung_mipi_dcphy_pll_round_rate()
1826 u8 prediv = 1; in samsung_mipi_dcphy_set_pll() local
[all …]
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| H A D | rk618_dsi.c | 213 u8 prediv; member
298 u32 fout, fref, prediv, fbdiv; in rk618_dsi_set_hs_clk() local
327 for (prediv = 1; prediv <= 12; prediv++) { in rk618_dsi_set_hs_clk()
331 if (fref % prediv) in rk618_dsi_set_hs_clk()
334 tmp = (u64)fout * prediv; in rk618_dsi_set_hs_clk()
345 do_div(tmp, prediv); in rk618_dsi_set_hs_clk()
350 phy->prediv = prediv; in rk618_dsi_set_hs_clk()
355 phy->prediv = prediv; in rk618_dsi_set_hs_clk()
401 REG_PREDIV(phy->prediv)); in rk618_dsi_phy_power_on()
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| H A D | inno_mipi_phy.c | 499 u8 *prediv, u16 *fbdiv) in inno_mipi_dphy_pll_round_rate() argument
533 *prediv = best_prediv; in inno_mipi_dphy_pll_round_rate()
676 u8 prediv = 0; in inno_mipi_dphy_set_pll() local
680 fout = inno_mipi_dphy_pll_round_rate(fin, rate, &prediv, &fbdiv); in inno_mipi_dphy_set_pll()
683 __func__, fin, fout, prediv, fbdiv); in inno_mipi_dphy_set_pll()
686 v = FBDIV_HI(fbdiv >> 8) | PREDIV(prediv); in inno_mipi_dphy_set_pll()
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| H A D | rockchip-inno-hdmi-phy.c | 178 u8 prediv; member
193 u8 prediv; member
598 v = POST_PLL_PRE_DIV(cfg->prediv); in inno_hdmi_phy_rk3228_power_on()
679 PCLK_VCO_DIV_5(cfg->vco_div_5_en) | PRE_PLL_PRE_DIV(cfg->prediv); in inno_hdmi_phy_rk3228_pre_pll_update()
745 val = (cfg->fbdiv >> 8) | cfg->prediv; in inno_hdmi_phy_rk3328_power_on()
750 val = (cfg->fbdiv >> 8) | cfg->prediv; in inno_hdmi_phy_rk3328_power_on()
839 inno_write(inno, 0xa1, cfg->prediv); in inno_hdmi_phy_rk3328_pre_pll_update()
934 val = cfg->prediv; in inno_hdmi_phy_rk3528_power_on()
1052 inno_write(inno, 0xa1, cfg->prediv); in inno_hdmi_phy_rk3528_pre_pll_update()
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| /rk3399_rockchip-uboot/arch/arm/mach-keystone/ |
| H A D | clock.c | 282 unsigned long mult = 1, prediv = 1, output_div = 2; in pll_freq_get() local
291 prediv = (tmp & CFG_PLLCTL0_PLLD_MASK) + 1; in pll_freq_get()
300 ret = ret / prediv / output_div * mult; in pll_freq_get()
332 prediv = (tmp & CFG_PLLCTL0_PLLD_MASK) + 1; in pll_freq_get()
337 ret = ((ret / prediv) * mult) / output_div; in pll_freq_get()
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| /rk3399_rockchip-uboot/arch/arm/mach-keystone/include/mach/ |
| H A D | clock_defs.h | 21 u32 prediv; /* 14 */ member
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| /rk3399_rockchip-uboot/drivers/ram/rockchip/ |
| H A D | sdram_rv1126.c | 567 u32 fbdiv, prediv, postdiv, postdiv_en; in phy_pll_set() local
582 prediv = 1; in phy_pll_set()
603 PHY_PREDIV_MASK << PHY_PREDIV_SHIFT, prediv); in phy_pll_set()
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