1*3d357619SMasahiro Yamada /* 2*3d357619SMasahiro Yamada * Copyright (C) 2011 3*3d357619SMasahiro Yamada * Heiko Schocher, DENX Software Engineering, hs@denx.de. 4*3d357619SMasahiro Yamada * 5*3d357619SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 6*3d357619SMasahiro Yamada */ 7*3d357619SMasahiro Yamada #ifndef _DV_PLL_DEFS_H_ 8*3d357619SMasahiro Yamada #define _DV_PLL_DEFS_H_ 9*3d357619SMasahiro Yamada 10*3d357619SMasahiro Yamada struct dv_pll_regs { 11*3d357619SMasahiro Yamada unsigned int pid; /* 0x00 */ 12*3d357619SMasahiro Yamada unsigned char rsvd0[224]; /* 0x04 */ 13*3d357619SMasahiro Yamada unsigned int rstype; /* 0xe4 */ 14*3d357619SMasahiro Yamada unsigned char rsvd1[24]; /* 0xe8 */ 15*3d357619SMasahiro Yamada unsigned int pllctl; /* 0x100 */ 16*3d357619SMasahiro Yamada unsigned char rsvd2[4]; /* 0x104 */ 17*3d357619SMasahiro Yamada unsigned int secctl; /* 0x108 */ 18*3d357619SMasahiro Yamada unsigned int rv; /* 0x10c */ 19*3d357619SMasahiro Yamada unsigned int pllm; /* 0x110 */ 20*3d357619SMasahiro Yamada unsigned int prediv; /* 0x114 */ 21*3d357619SMasahiro Yamada unsigned int plldiv1; /* 0x118 */ 22*3d357619SMasahiro Yamada unsigned int plldiv2; /* 0x11c */ 23*3d357619SMasahiro Yamada unsigned int plldiv3; /* 0x120 */ 24*3d357619SMasahiro Yamada unsigned int oscdiv1; /* 0x124 */ 25*3d357619SMasahiro Yamada unsigned int postdiv; /* 0x128 */ 26*3d357619SMasahiro Yamada unsigned int bpdiv; /* 0x12c */ 27*3d357619SMasahiro Yamada unsigned char rsvd5[8]; /* 0x130 */ 28*3d357619SMasahiro Yamada unsigned int pllcmd; /* 0x138 */ 29*3d357619SMasahiro Yamada unsigned int pllstat; /* 0x13c */ 30*3d357619SMasahiro Yamada unsigned int alnctl; /* 0x140 */ 31*3d357619SMasahiro Yamada unsigned int dchange; /* 0x144 */ 32*3d357619SMasahiro Yamada unsigned int cken; /* 0x148 */ 33*3d357619SMasahiro Yamada unsigned int ckstat; /* 0x14c */ 34*3d357619SMasahiro Yamada unsigned int systat; /* 0x150 */ 35*3d357619SMasahiro Yamada unsigned char rsvd6[12]; /* 0x154 */ 36*3d357619SMasahiro Yamada unsigned int plldiv4; /* 0x160 */ 37*3d357619SMasahiro Yamada unsigned int plldiv5; /* 0x164 */ 38*3d357619SMasahiro Yamada unsigned int plldiv6; /* 0x168 */ 39*3d357619SMasahiro Yamada unsigned int plldiv7; /* 0x16C */ 40*3d357619SMasahiro Yamada unsigned int plldiv8; /* 0x170 */ 41*3d357619SMasahiro Yamada unsigned int plldiv9; /* 0x174 */ 42*3d357619SMasahiro Yamada }; 43*3d357619SMasahiro Yamada 44*3d357619SMasahiro Yamada #define PLL_MASTER_LOCK (1 << 4) 45*3d357619SMasahiro Yamada 46*3d357619SMasahiro Yamada #define PLLCTL_CLOCK_MODE_SHIFT 8 47*3d357619SMasahiro Yamada #define PLLCTL_PLLEN (1 << 0) 48*3d357619SMasahiro Yamada #define PLLCTL_PLLPWRDN (1 << 1) 49*3d357619SMasahiro Yamada #define PLLCTL_PLLRST (1 << 3) 50*3d357619SMasahiro Yamada #define PLLCTL_PLLDIS (1 << 4) 51*3d357619SMasahiro Yamada #define PLLCTL_PLLENSRC (1 << 5) 52*3d357619SMasahiro Yamada #define PLLCTL_RES_9 (1 << 8) 53*3d357619SMasahiro Yamada #define PLLCTL_EXTCLKSRC (1 << 9) 54*3d357619SMasahiro Yamada 55*3d357619SMasahiro Yamada #define PLL_DIVEN (1 << 15) 56*3d357619SMasahiro Yamada #define PLL_POSTDEN PLL_DIVEN 57*3d357619SMasahiro Yamada 58*3d357619SMasahiro Yamada #define PLL_SCSCFG3_DIV45PENA (1 << 2) 59*3d357619SMasahiro Yamada #define PLL_SCSCFG3_EMA_CLKSRC (1 << 1) 60*3d357619SMasahiro Yamada 61*3d357619SMasahiro Yamada #define PLL_RSTYPE_POR (1 << 0) 62*3d357619SMasahiro Yamada #define PLL_RSTYPE_XWRST (1 << 1) 63*3d357619SMasahiro Yamada 64*3d357619SMasahiro Yamada #define PLLSECCTL_TINITZ (1 << 16) 65*3d357619SMasahiro Yamada #define PLLSECCTL_TENABLE (1 << 17) 66*3d357619SMasahiro Yamada #define PLLSECCTL_TENABLEDIV (1 << 18) 67*3d357619SMasahiro Yamada #define PLLSECCTL_STOPMODE (1 << 22) 68*3d357619SMasahiro Yamada 69*3d357619SMasahiro Yamada #define PLLCMD_GOSET (1 << 0) 70*3d357619SMasahiro Yamada #define PLLCMD_GOSTAT (1 << 0) 71*3d357619SMasahiro Yamada 72*3d357619SMasahiro Yamada #define PLL0_LOCK 0x07000000 73*3d357619SMasahiro Yamada #define PLL1_LOCK 0x07000000 74*3d357619SMasahiro Yamada 75*3d357619SMasahiro Yamada #define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE) 76*3d357619SMasahiro Yamada #define dv_pll1_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL1_BASE) 77*3d357619SMasahiro Yamada 78*3d357619SMasahiro Yamada #define ARM_PLLDIV (offsetof(struct dv_pll_regs, plldiv2)) 79*3d357619SMasahiro Yamada #define DDR_PLLDIV (offsetof(struct dv_pll_regs, plldiv7)) 80*3d357619SMasahiro Yamada #define SPI_PLLDIV (offsetof(struct dv_pll_regs, plldiv4)) 81*3d357619SMasahiro Yamada 82*3d357619SMasahiro Yamada unsigned int davinci_clk_get(unsigned int div); 83*3d357619SMasahiro Yamada #endif /* _DV_PLL_DEFS_H_ */ 84