Home
last modified time | relevance | path

Searched refs:pmu (Results 1 – 25 of 84) sorted by relevance

1234

/rk3399_rockchip-uboot/drivers/power/
H A Dftpmu010.c19 static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; in ftpmu010_32768osc_enable() local
23 oscc = readl(&pmu->OSCC); in ftpmu010_32768osc_enable()
25 writel(oscc, &pmu->OSCC); in ftpmu010_32768osc_enable()
28 while (!(readl(&pmu->OSCC) & FTPMU010_OSCC_OSCL_STABLE)) in ftpmu010_32768osc_enable()
32 oscc = readl(&pmu->OSCC); in ftpmu010_32768osc_enable()
34 writel(oscc, &pmu->OSCC); in ftpmu010_32768osc_enable()
40 static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; in ftpmu010_mfpsr_select_dev() local
43 mfpsr = readl(&pmu->MFPSR); in ftpmu010_mfpsr_select_dev()
45 writel(mfpsr, &pmu->MFPSR); in ftpmu010_mfpsr_select_dev()
50 static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; in ftpmu010_mfpsr_diselect_dev() local
[all …]
/rk3399_rockchip-uboot/arch/x86/lib/
H A Dpmu.c84 struct pmu_mid *pmu; in pmu_turn_power() local
92 pmu = dev_get_priv(dev); in pmu_turn_power()
94 return pmu_power_lss(pmu->regs, lss, on); in pmu_turn_power()
99 struct pmu_mid *pmu = dev_get_priv(dev); in pmu_mid_probe() local
101 pmu->regs = syscon_get_first_range(X86_SYSCON_PMU); in pmu_mid_probe()
H A DMakefile35 obj-$(CONFIG_INTEL_MID) += pmu.o
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dbcm2835.dtsi21 arm-pmu {
22 compatible = "arm,arm1176-pmu";
H A Ddra72x.dtsi31 pmu {
32 compatible = "arm,cortex-a15-pmu";
H A Dbcm2836.dtsi19 arm-pmu {
20 compatible = "arm,cortex-a7-pmu";
H A Ddra74x.dtsi47 pmu {
48 compatible = "arm,cortex-a15-pmu";
H A Drk3xxx.dtsi221 pmu: pmu@20004000 { label
222 compatible = "rockchip,rk3066-pmu", "syscon";
238 rockchip,pmu = <&pmu>;
H A Dexynos4210.dtsi79 pmu {
80 compatible = "arm,cortex-a9-pmu";
H A Drk3399-u-boot.dtsi41 &pmu {
H A Drk3288-u-boot.dtsi29 &pmu {
H A Drk3288.dtsi57 rockchip,pmu = <&pmu>;
523 rockchip,pmu = <&pmu>;
630 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
634 pmu: power-management@ff730000 { label
635 compatible = "rockchip,rk3288-pmu", "syscon";
1032 rockchip,pmu = <&pmu>;
1592 rockchip,pmu = <&pmu>;
H A Drk3188.dtsi169 rockchip,pmu = <&pmu>;
553 &pmu {
554 compatible = "rockchip,rk3188-pmu", "syscon";
H A Dkeystone.dtsi63 pmu {
64 compatible = "arm,cortex-a15-pmu";
/rk3399_rockchip-uboot/board/theobroma-systems/puma_rk3399/
H A Dfit_spl_atf.its35 pmu {
38 type = "pmu-firmware";
55 loadables = "uboot", "pmu";
/rk3399_rockchip-uboot/arch/arm/mach-exynos/
H A Dpower.c15 struct exynos4_power *pmu = in exynos4_mipi_phy_control() local
20 addr = (unsigned int)&pmu->mipi_phy0_control; in exynos4_mipi_phy_control()
22 addr = (unsigned int)&pmu->mipi_phy1_control; in exynos4_mipi_phy_control()
H A Ddmc_init_ddr3.c450 struct exynos5_power *pmu; in ddr3_mem_ctrl_init() local
465 pmu = (struct exynos5_power *)EXYNOS5420_POWER_BASE; in ddr3_mem_ctrl_init()
804 dmc_set_read_offset_value(phy0_ctrl, readl(&pmu->pmu_spare1)); in ddr3_mem_ctrl_init()
805 dmc_set_read_offset_value(phy1_ctrl, readl(&pmu->pmu_spare2)); in ddr3_mem_ctrl_init()
812 writel(dmc_get_read_offset_value(phy0_ctrl), &pmu->pmu_spare1); in ddr3_mem_ctrl_init()
813 writel(dmc_get_read_offset_value(phy1_ctrl), &pmu->pmu_spare2); in ddr3_mem_ctrl_init()
/rk3399_rockchip-uboot/doc/device-tree-bindings/pinctrl/
H A Drockchip,pinctrl.txt29 - rockchip,pmu: phandle referencing a syscon providing the pmu registers
37 Use rockchip,grf and rockchip,pmu described above instead.
56 rockchip,pmu described above instead
124 rockchip,pmu = <&pmu>;
/rk3399_rockchip-uboot/arch/x86/dts/
H A Dedison.dts80 pmu: power@ff00b000 { label
81 compatible = "intel,pmu-mid";
/rk3399_rockchip-uboot/doc/device-tree-bindings/clock/
H A Drockchip,rk3288-dmc.txt6 - rockchip,pmu: this driver should access pmu regs, so need get pmu here
117 rockchip,pmu = <&pmu>;
/rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra20/
H A DMakefile19 obj-$(CONFIG_TEGRA_PMU) += pmu.o
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dsdram_rv1108.h44 struct rv1108_pmu *pmu; member
H A Dsdram_rk3308.h77 struct rk3308_pmu *pmu; member
/rk3399_rockchip-uboot/drivers/ram/rockchip/
H A Dsdram_rv1108.c32 writel(DDR_IO_RET_EN, &priv->pmu->sft_con); in enable_ddr_io_ret()
244 sdram_priv->pmu = get_base_addr((void *)dtplat->reg, 6); in sdram_init()
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3066/
H A Dsdram_rk3066.c43 struct rk3188_pmu *pmu; member
551 writel(sys_reg, &dram->pmu->sys_reg[2]); in dram_all_config()
882 priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); in rk3066_dmc_probe()
907 (phys_addr_t)&priv->pmu->sys_reg[2]); in rk3066_dmc_probe()

1234