1*495f3774SAndy Shevchenko/* 2*495f3774SAndy Shevchenko * Copyright (c) 2017 Intel Corporation 3*495f3774SAndy Shevchenko * 4*495f3774SAndy Shevchenko * SPDX-License-Identifier: GPL-2.0+ 5*495f3774SAndy Shevchenko */ 6*495f3774SAndy Shevchenko 7*495f3774SAndy Shevchenko/dts-v1/; 8*495f3774SAndy Shevchenko 9*495f3774SAndy Shevchenko#include <dt-bindings/gpio/x86-gpio.h> 10*495f3774SAndy Shevchenko#include <dt-bindings/interrupt-router/intel-irq.h> 11*495f3774SAndy Shevchenko 12*495f3774SAndy Shevchenko/include/ "skeleton.dtsi" 13*495f3774SAndy Shevchenko/include/ "rtc.dtsi" 14*495f3774SAndy Shevchenko/include/ "tsc_timer.dtsi" 15*495f3774SAndy Shevchenko 16*495f3774SAndy Shevchenko/ { 17*495f3774SAndy Shevchenko model = "Intel Edison"; 18*495f3774SAndy Shevchenko compatible = "intel,edison"; 19*495f3774SAndy Shevchenko 20*495f3774SAndy Shevchenko aliases { 21*495f3774SAndy Shevchenko serial0 = &serial0; 22*495f3774SAndy Shevchenko }; 23*495f3774SAndy Shevchenko 24*495f3774SAndy Shevchenko chosen { 25*495f3774SAndy Shevchenko stdout-path = &serial0; 26*495f3774SAndy Shevchenko }; 27*495f3774SAndy Shevchenko 28*495f3774SAndy Shevchenko cpus { 29*495f3774SAndy Shevchenko #address-cells = <1>; 30*495f3774SAndy Shevchenko #size-cells = <0>; 31*495f3774SAndy Shevchenko 32*495f3774SAndy Shevchenko cpu@0 { 33*495f3774SAndy Shevchenko device_type = "cpu"; 34*495f3774SAndy Shevchenko compatible = "cpu-x86"; 35*495f3774SAndy Shevchenko reg = <0>; 36*495f3774SAndy Shevchenko intel,apic-id = <0>; 37*495f3774SAndy Shevchenko }; 38*495f3774SAndy Shevchenko 39*495f3774SAndy Shevchenko cpu@1 { 40*495f3774SAndy Shevchenko device_type = "cpu"; 41*495f3774SAndy Shevchenko compatible = "cpu-x86"; 42*495f3774SAndy Shevchenko reg = <1>; 43*495f3774SAndy Shevchenko intel,apic-id = <2>; 44*495f3774SAndy Shevchenko }; 45*495f3774SAndy Shevchenko }; 46*495f3774SAndy Shevchenko 47*495f3774SAndy Shevchenko pci { 48*495f3774SAndy Shevchenko compatible = "pci-x86"; 49*495f3774SAndy Shevchenko #address-cells = <3>; 50*495f3774SAndy Shevchenko #size-cells = <2>; 51*495f3774SAndy Shevchenko u-boot,dm-pre-reloc; 52*495f3774SAndy Shevchenko ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000 53*495f3774SAndy Shevchenko 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 54*495f3774SAndy Shevchenko 0x01000000 0x0 0x2000 0x2000 0 0xe000>; 55*495f3774SAndy Shevchenko }; 56*495f3774SAndy Shevchenko 57*495f3774SAndy Shevchenko serial0: serial@ff010180 { 58*495f3774SAndy Shevchenko compatible = "intel,mid-uart"; 59*495f3774SAndy Shevchenko reg = <0xff010180 0x100>; 60*495f3774SAndy Shevchenko reg-shift = <0>; 61*495f3774SAndy Shevchenko clock-frequency = <29491200>; 62*495f3774SAndy Shevchenko current-speed = <115200>; 63*495f3774SAndy Shevchenko }; 64*495f3774SAndy Shevchenko 65*495f3774SAndy Shevchenko emmc: mmc@ff3fc000 { 66*495f3774SAndy Shevchenko compatible = "intel,sdhci-tangier"; 67*495f3774SAndy Shevchenko reg = <0xff3fc000 0x1000>; 68*495f3774SAndy Shevchenko }; 69*495f3774SAndy Shevchenko 70*495f3774SAndy Shevchenko/* 71*495f3774SAndy Shevchenko * FIXME: For now U-Boot DM model doesn't allow to power up this controller. 72*495f3774SAndy Shevchenko * Enabling it will make U-Boot hang. 73*495f3774SAndy Shevchenko * 74*495f3774SAndy Shevchenko sdcard: mmc@ff3fa000 { 75*495f3774SAndy Shevchenko compatible = "intel,sdhci-tangier"; 76*495f3774SAndy Shevchenko reg = <0xff3fa000 0x1000>; 77*495f3774SAndy Shevchenko }; 78*495f3774SAndy Shevchenko */ 79*495f3774SAndy Shevchenko 80*495f3774SAndy Shevchenko pmu: power@ff00b000 { 81*495f3774SAndy Shevchenko compatible = "intel,pmu-mid"; 82*495f3774SAndy Shevchenko reg = <0xff00b000 0x1000>; 83*495f3774SAndy Shevchenko }; 84*495f3774SAndy Shevchenko 85*495f3774SAndy Shevchenko scu: ipc@ff009000 { 86*495f3774SAndy Shevchenko compatible = "intel,scu-ipc"; 87*495f3774SAndy Shevchenko reg = <0xff009000 0x1000>; 88*495f3774SAndy Shevchenko }; 89*495f3774SAndy Shevchenko}; 90