1*e5520e18SMugunthan V N/* 2*e5520e18SMugunthan V N * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ 3*e5520e18SMugunthan V N * 4*e5520e18SMugunthan V N * This program is free software; you can redistribute it and/or modify 5*e5520e18SMugunthan V N * it under the terms of the GNU General Public License version 2 as 6*e5520e18SMugunthan V N * published by the Free Software Foundation. 7*e5520e18SMugunthan V N * Based on "omap4.dtsi" 8*e5520e18SMugunthan V N */ 9*e5520e18SMugunthan V N 10*e5520e18SMugunthan V N#include "dra7.dtsi" 11*e5520e18SMugunthan V N 12*e5520e18SMugunthan V N/ { 13*e5520e18SMugunthan V N compatible = "ti,dra742", "ti,dra74", "ti,dra7"; 14*e5520e18SMugunthan V N 15*e5520e18SMugunthan V N cpus { 16*e5520e18SMugunthan V N #address-cells = <1>; 17*e5520e18SMugunthan V N #size-cells = <0>; 18*e5520e18SMugunthan V N 19*e5520e18SMugunthan V N cpu0: cpu@0 { 20*e5520e18SMugunthan V N device_type = "cpu"; 21*e5520e18SMugunthan V N compatible = "arm,cortex-a15"; 22*e5520e18SMugunthan V N reg = <0>; 23*e5520e18SMugunthan V N 24*e5520e18SMugunthan V N operating-points = < 25*e5520e18SMugunthan V N /* kHz uV */ 26*e5520e18SMugunthan V N 1000000 1060000 27*e5520e18SMugunthan V N 1176000 1160000 28*e5520e18SMugunthan V N >; 29*e5520e18SMugunthan V N 30*e5520e18SMugunthan V N clocks = <&dpll_mpu_ck>; 31*e5520e18SMugunthan V N clock-names = "cpu"; 32*e5520e18SMugunthan V N 33*e5520e18SMugunthan V N clock-latency = <300000>; /* From omap-cpufreq driver */ 34*e5520e18SMugunthan V N 35*e5520e18SMugunthan V N /* cooling options */ 36*e5520e18SMugunthan V N cooling-min-level = <0>; 37*e5520e18SMugunthan V N cooling-max-level = <2>; 38*e5520e18SMugunthan V N #cooling-cells = <2>; /* min followed by max */ 39*e5520e18SMugunthan V N }; 40*e5520e18SMugunthan V N cpu@1 { 41*e5520e18SMugunthan V N device_type = "cpu"; 42*e5520e18SMugunthan V N compatible = "arm,cortex-a15"; 43*e5520e18SMugunthan V N reg = <1>; 44*e5520e18SMugunthan V N }; 45*e5520e18SMugunthan V N }; 46*e5520e18SMugunthan V N 47*e5520e18SMugunthan V N pmu { 48*e5520e18SMugunthan V N compatible = "arm,cortex-a15-pmu"; 49*e5520e18SMugunthan V N interrupt-parent = <&wakeupgen>; 50*e5520e18SMugunthan V N interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 51*e5520e18SMugunthan V N <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 52*e5520e18SMugunthan V N }; 53*e5520e18SMugunthan V N 54*e5520e18SMugunthan V N ocp { 55*e5520e18SMugunthan V N omap_dwc3_4: omap_dwc3_4@48940000 { 56*e5520e18SMugunthan V N compatible = "ti,dwc3"; 57*e5520e18SMugunthan V N ti,hwmods = "usb_otg_ss4"; 58*e5520e18SMugunthan V N reg = <0x48940000 0x10000>; 59*e5520e18SMugunthan V N interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; 60*e5520e18SMugunthan V N #address-cells = <1>; 61*e5520e18SMugunthan V N #size-cells = <1>; 62*e5520e18SMugunthan V N utmi-mode = <2>; 63*e5520e18SMugunthan V N ranges; 64*e5520e18SMugunthan V N status = "disabled"; 65*e5520e18SMugunthan V N usb4: usb@48950000 { 66*e5520e18SMugunthan V N compatible = "snps,dwc3"; 67*e5520e18SMugunthan V N reg = <0x48950000 0x17000>; 68*e5520e18SMugunthan V N interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 69*e5520e18SMugunthan V N tx-fifo-resize; 70*e5520e18SMugunthan V N maximum-speed = "high-speed"; 71*e5520e18SMugunthan V N dr_mode = "otg"; 72*e5520e18SMugunthan V N }; 73*e5520e18SMugunthan V N }; 74*e5520e18SMugunthan V N }; 75*e5520e18SMugunthan V N}; 76*e5520e18SMugunthan V N 77*e5520e18SMugunthan V N&dss { 78*e5520e18SMugunthan V N reg = <0x58000000 0x80>, 79*e5520e18SMugunthan V N <0x58004054 0x4>, 80*e5520e18SMugunthan V N <0x58004300 0x20>, 81*e5520e18SMugunthan V N <0x58005054 0x4>, 82*e5520e18SMugunthan V N <0x58005300 0x20>; 83*e5520e18SMugunthan V N reg-names = "dss", "pll1_clkctrl", "pll1", 84*e5520e18SMugunthan V N "pll2_clkctrl", "pll2"; 85*e5520e18SMugunthan V N 86*e5520e18SMugunthan V N clocks = <&dss_dss_clk>, 87*e5520e18SMugunthan V N <&dss_video1_clk>, 88*e5520e18SMugunthan V N <&dss_video2_clk>; 89*e5520e18SMugunthan V N clock-names = "fck", "video1_clk", "video2_clk"; 90*e5520e18SMugunthan V N}; 91