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Searched refs:pmic_clrsetbits (Results 1 – 22 of 22) sorted by relevance

/rk3399_rockchip-uboot/board/freescale/mx6sllevk/
H A Dmx6sllevk.c79 pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b); in power_init_board()
82 pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40); in power_init_board()
85 pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x1b); in power_init_board()
88 pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40); in power_init_board()
/rk3399_rockchip-uboot/drivers/power/regulator/
H A Dsy7636a_regulator.c32 ret = pmic_clrsetbits(pmic, SY7636A_REG_OPERATION_MODE_CRL, in sy7636a_set_enable()
35 ret = pmic_clrsetbits(pmic, SY7636A_REG_OPERATION_MODE_CRL, in sy7636a_set_enable()
68 ret = pmic_clrsetbits(pmic, SY7636A_REG_OPERATION_MODE_CRL, in sy7636a_set_value()
85 ret = pmic_clrsetbits(pmic, SY7636A_REG_OPERATION_MODE_CRL, 0, in sy7636a_set_value()
H A Drk8xx.c401 pmic_clrsetbits(pmic, info->vsel_reg, mask, val); in _buck_set_value()
402 return pmic_clrsetbits(pmic, RK816_REG_DCDC_EN2, 1 << 7, 1 << 7); in _buck_set_value()
404 return pmic_clrsetbits(pmic, info->vsel_reg, mask, val); in _buck_set_value()
443 ret = pmic_clrsetbits(pmic, REG_DCDC_ILMAX, in _buck_set_enable()
448 ret = pmic_clrsetbits(pmic, REG_DCDC_EN, mask, in _buck_set_enable()
493 return pmic_clrsetbits(pmic, info->vsel_sleep_reg, mask, val); in _buck_set_suspend_value()
682 return pmic_clrsetbits(pmic, info->config_reg, ramp_mask, ramp_value); in _buck_set_ramp_delay()
695 ret = pmic_clrsetbits(pmic, RK816_REG_DCDC_SLP_EN, mask, in _buck_set_suspend_enable()
701 ret = pmic_clrsetbits(pmic, RK806_BUCK_SUSPEND_EN, mask, in _buck_set_suspend_enable()
708 ret = pmic_clrsetbits(pmic, RK806_NLDO_SUSPEND_EN, mask, in _buck_set_suspend_enable()
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H A Drk801_regulator.c372 ret = pmic_clrsetbits(pmic, reg, desc->vsel_mask, sel); in rk801_regulator_set_value()
381 ret = pmic_clrsetbits(pmic, reg1, desc->vsel_mask, sel); in rk801_regulator_set_value()
383 ret = pmic_clrsetbits(pmic, reg0, desc->vsel_mask, sel); in rk801_regulator_set_value()
407 return pmic_clrsetbits(pmic, reg, desc->vsel_mask, sel); in rk801_regulator_set_value()
452 return pmic_clrsetbits(pmic, desc->enable_reg, desc->enable_mask, val); in rk801_regulator_set_enable()
467 return pmic_clrsetbits(pmic, RK801_POWER_SLP_EN_REG, in rk801_regulator_set_suspend_enable()
612 ret = pmic_clrsetbits(pmic, RK801_SYS_CFG2_REG, in rk801_buck_probe()
617 ret = pmic_clrsetbits(pmic, RK801_SLEEP_CFG_REG, in rk801_buck_probe()
623 ret = pmic_clrsetbits(pmic, RK801_SLP_LP_CONFIG_REG, in rk801_buck_probe()
H A Das3722_regulator.c33 ret = pmic_clrsetbits(pmic, AS3722_SD_CONTROL, 0, 1 << sd); in stepdown_set_enable()
75 ret = pmic_clrsetbits(pmic, AS3722_LDO_CONTROL, 0, 1 << ldo); in ldo_set_enable()
H A Dact8846.c107 return pmic_clrsetbits(dev->parent, addr_vol[reg], LDO_VOL_MASK, val); in reg_set_value()
114 return pmic_clrsetbits(dev->parent, addr_ctl[reg], LDO_EN_MASK, in reg_set_enable()
H A Dpfuze100.c364 return pmic_clrsetbits(dev->parent, desc->vsel_reg, in pfuze100_regulator_mode()
368 val = pmic_clrsetbits(dev->parent, in pfuze100_regulator_mode()
374 val = pmic_clrsetbits(dev->parent, desc->vsel_reg, in pfuze100_regulator_mode()
495 return pmic_clrsetbits(dev->parent, desc->vsel_reg, in pfuze100_regulator_val()
502 return pmic_clrsetbits(dev->parent, desc->vsel_reg, in pfuze100_regulator_val()
H A Ds5m8767.c127 ret = pmic_clrsetbits(dev->parent, param->vol_addr, in reg_set_value()
182 ret = pmic_clrsetbits(dev->parent, param->reg_enaddr, in reg_set_enable()
H A Dfp9931_regulator.c34 ret = pmic_clrsetbits(pmic, FP9931_CONTROL_REG1, 0, CONTROL_REG1_V3P3_EN); in fp9931_vcom_set_enable()
/rk3399_rockchip-uboot/board/freescale/mx6sxsabreauto/
H A Dmx6sxsabreauto.c157 pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b); in power_init_board()
160 pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40); in power_init_board()
163 pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x20); in power_init_board()
166 pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40); in power_init_board()
/rk3399_rockchip-uboot/board/samsung/common/
H A Dexynos5-dt.c99 ret = pmic_clrsetbits(dev, MAX77686_REG_PMIC_32KHZ, 0, in exynos_power_init()
103 ret = pmic_clrsetbits(dev, MAX77686_REG_PMIC_BBAT, 0, in exynos_power_init()
/rk3399_rockchip-uboot/board/freescale/mx6slevk/
H A Dmx6slevk.c186 pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b); in power_init_board()
189 pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40); in power_init_board()
192 pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x1b); in power_init_board()
195 pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40); in power_init_board()
/rk3399_rockchip-uboot/drivers/gpio/
H A Dpm8916_gpio.c64 ret = pmic_clrsetbits(dev->parent, gpio_base + REG_EN_CTL, in pm8916_gpio_set_direction()
102 return pmic_clrsetbits(dev->parent, gpio_base + REG_EN_CTL, 0, in pm8916_gpio_set_direction()
159 return pmic_clrsetbits(dev->parent, gpio_base + REG_CTL, in pm8916_gpio_set_value()
/rk3399_rockchip-uboot/board/nvidia/jetson-tk1/
H A Djetson-tk1.c50 err = pmic_clrsetbits(pmic, AS3722_SD_CONTROL, 0, 1 << sd); in as3722_sd_enable()
/rk3399_rockchip-uboot/board/toradex/colibri_imx7/
H A Dcolibri_imx7.c361 pmic_clrsetbits(dev, RN5T567_NOETIMSETCNT, 0x7, 0); in power_init_board()
369 pmic_clrsetbits(dev, RN5T567_DC2CTL, 0x2, 0); in power_init_board()
377 pmic_clrsetbits(dev, RN5T567_LDODIS1, 0x2, 0); in power_init_board()
/rk3399_rockchip-uboot/drivers/power/pmic/
H A Ds5m8767.c52 return pmic_clrsetbits(dev, S5M8767_EN32KHZ_CP, 0, 1 << 1); in s5m8767_enable_32khz_cp()
H A Dpmic-uclass.c179 int pmic_clrsetbits(struct udevice *dev, uint reg, uint clr, uint set) in pmic_clrsetbits() function
H A Dpmic_rk801.c192 ret = pmic_clrsetbits(dev, in rk801_probe()
H A Drk8xx.c965 ret = pmic_clrsetbits(dev, in rk8xx_probe()
977 ret = pmic_clrsetbits(dev, in rk8xx_probe()
/rk3399_rockchip-uboot/board/freescale/mx7dsabresd/
H A Dmx7dsabresd.c355 pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1); in power_init_board()
361 pmic_clrsetbits(dev, PFUZE3000_VLD4CTL, 0xF, 0xA); in power_init_board()
/rk3399_rockchip-uboot/include/power/
H A Dpmic.h303 int pmic_clrsetbits(struct udevice *dev, uint reg, uint clr, uint set);
/rk3399_rockchip-uboot/drivers/sound/
H A Drk817_codec.c59 return pmic_clrsetbits(dev, reg, mask, value); in snd_soc_update_bits()