Searched refs:pllcr (Results 1 – 9 of 9) sorted by relevance
30 unsigned long pllcr; in get_clocks() local37 pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ in get_clocks()39 pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ in get_clocks()44 pllcr = CONFIG_SYS_PLLCR; in get_clocks()49 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ in get_clocks()50 pllcr ^= 0x00000001; /* Set pll bypass to 1 */ in get_clocks()51 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ in get_clocks()
17 .pllcr = 0x000DC000ul,68 .pllcr = 0x000DC000ul,
16 .pllcr = 0x0001C000ul,
16 unsigned int pllcr; member
29 u8 pllcr; member
22 debug_ddr_cfg("\npllcr 0x%08X\n", ptr->pllcr); in dump_phy_config()305 spd_cb->phy_cfg.pllcr = (spd->freqsel & 3) << 18 | 0xE << 13; in init_ddr3param()
33 __raw_writel(phy_cfg->pllcr, base + KS2_DDRPHY_PLLCR_OFFSET); in ddr3_init_ddrphy()
98 u32 pllcr; /* 0x20 PLL control register */ member
742 setbits_le32(&mctl_phy->pllcr, 0x3 << 19); /* PLL frequency select */ in mctl_channel_init()744 setbits_le32(&mctl_phy->pllcr, in mctl_channel_init()