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Searched refs:pctl_base (Results 1 – 7 of 7) sorted by relevance

/rk3399_rockchip-uboot/drivers/ram/rockchip/
H A Dsdram_pctl_px30.c16 void pctl_read_mr(void __iomem *pctl_base, u32 rank, u32 mr_num) in pctl_read_mr() argument
18 writel((rank << 4) | (1 << 0), pctl_base + DDR_PCTL2_MRCTRL0); in pctl_read_mr()
19 writel((mr_num << 8), pctl_base + DDR_PCTL2_MRCTRL1); in pctl_read_mr()
20 setbits_le32(pctl_base + DDR_PCTL2_MRCTRL0, 1u << 31); in pctl_read_mr()
21 while (readl(pctl_base + DDR_PCTL2_MRCTRL0) & (1u << 31)) in pctl_read_mr()
23 while (readl(pctl_base + DDR_PCTL2_MRSTAT) & PCTL2_MR_WR_BUSY) in pctl_read_mr()
32 int pctl_write_mr(void __iomem *pctl_base, u32 rank, u32 mr_num, u32 arg, in pctl_write_mr() argument
35 while (readl(pctl_base + DDR_PCTL2_MRSTAT) & PCTL2_MR_WR_BUSY) in pctl_write_mr()
39 pctl_base + DDR_PCTL2_MRCTRL0); in pctl_write_mr()
40 writel(arg, pctl_base + DDR_PCTL2_MRCTRL1); in pctl_write_mr()
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H A Dsdram_px30.c173 void __iomem *pctl_base = dram->pctl; in set_ctl_address_map() local
189 writel(0x1f, pctl_base + DDR_PCTL2_ADDRMAP0); in set_ctl_address_map()
191 writel(cs_pst - 8, pctl_base + DDR_PCTL2_ADDRMAP0); in set_ctl_address_map()
203 sdram_copy_to_reg((u32 *)(pctl_base + DDR_PCTL2_ADDRMAP1), in set_ctl_address_map()
211 clrsetbits_le32(pctl_base + DDR_PCTL2_ADDRMAP6 + in set_ctl_address_map()
219 setbits_le32(pctl_base + DDR_PCTL2_ADDRMAP6, 1 << 31); in set_ctl_address_map()
221 setbits_le32(pctl_base + DDR_PCTL2_PCCFG, 1 << 8); in set_ctl_address_map()
276 void __iomem *pctl_base = dram->pctl; in data_training() local
282 pwrctl = readl(pctl_base + DDR_PCTL2_PWRCTL); in data_training()
283 writel(0, pctl_base + DDR_PCTL2_PWRCTL); in data_training()
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H A Dsdram_rv1126.c503 void __iomem *pctl_base = dram->pctl; in sw_set_req() local
506 writel(PCTL2_SW_DONE_CLEAR, pctl_base + DDR_PCTL2_SWCTL); in sw_set_req()
511 void __iomem *pctl_base = dram->pctl; in sw_set_ack() local
514 writel(PCTL2_SW_DONE, pctl_base + DDR_PCTL2_SWCTL); in sw_set_ack()
517 if (readl(pctl_base + DDR_PCTL2_SWSTAT) & in sw_set_ack()
527 void __iomem *pctl_base = dram->pctl; in set_ctl_address_map() local
546 sdram_copy_to_reg((u32 *)(pctl_base + DDR_PCTL2_ADDRMAP0), in set_ctl_address_map()
551 setbits_le32(pctl_base + DDR_PCTL2_ADDRMAP6 + in set_ctl_address_map()
556 setbits_le32(pctl_base + DDR_PCTL2_ADDRMAP6, 1 << 31); in set_ctl_address_map()
558 setbits_le32(pctl_base + DDR_PCTL2_PCCFG, 1 << 8); in set_ctl_address_map()
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H A Dsdram_rk3328.c223 void __iomem *pctl_base = dram->pctl; in set_ctl_address_map() local
225 sdram_copy_to_reg((u32 *)(pctl_base + DDR_PCTL2_ADDRMAP0), in set_ctl_address_map()
228 setbits_le32(pctl_base + DDR_PCTL2_ADDRMAP6, 1 << 31); in set_ctl_address_map()
230 setbits_le32(pctl_base + DDR_PCTL2_PCCFG, 1 << 8); in set_ctl_address_map()
233 clrsetbits_le32(pctl_base + DDR_PCTL2_ADDRMAP0, 0x1f, 0x1f); in set_ctl_address_map()
238 void __iomem *pctl_base = dram->pctl; in data_training() local
244 pwrctl = readl(pctl_base + DDR_PCTL2_PWRCTL); in data_training()
245 writel(0, pctl_base + DDR_PCTL2_PWRCTL); in data_training()
254 writel(pwrctl, pctl_base + DDR_PCTL2_PWRCTL); in data_training()
325 void __iomem *pctl_base = dram->pctl; in enable_low_power() local
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H A Dsdram_common.c13 u32 __weak pctl_dis_zqcs_aref(void __iomem *pctl_base) in pctl_dis_zqcs_aref() argument
17 void __weak pctl_rest_zqcs_aref(void __iomem *pctl_base, u32 dis_auto_zq) in pctl_rest_zqcs_aref() argument
21 void __weak send_a_refresh(void __iomem *pctl_base, u32 cs) in send_a_refresh() argument
282 int sdram_detect_bank(struct sdram_cap_info *cap_info, void __iomem *pctl_base, in sdram_detect_bank() argument
291 dis_auto_ref = pctl_dis_zqcs_aref(pctl_base); in sdram_detect_bank()
295 send_a_refresh(pctl_base, 0x1); in sdram_detect_bank()
298 send_a_refresh(pctl_base, 0x1); in sdram_detect_bank()
307 send_a_refresh(pctl_base, 0x1); in sdram_detect_bank()
308 pctl_rest_zqcs_aref(pctl_base, dis_auto_ref); in sdram_detect_bank()
314 int sdram_detect_bg(struct sdram_cap_info *cap_info, void __iomem *pctl_base, in sdram_detect_bg() argument
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/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dsdram_pctl_px30.h253 void pctl_read_mr(void __iomem *pctl_base, u32 rank, u32 mr_num);
254 int pctl_write_mr(void __iomem *pctl_base, u32 rank, u32 mr_num, u32 arg,
256 int pctl_write_vrefdq(void __iomem *pctl_base, u32 rank, u32 vrefrate,
259 u32 pctl_dis_zqcs_aref(void __iomem *pctl_base);
260 void pctl_rest_zqcs_aref(void __iomem *pctl_base, u32 dis_auto_zq);
265 int pctl_cfg(void __iomem *pctl_base, struct ddr_pctl_regs *pctl_regs,
268 void send_a_refresh(void __iomem *pctl_base, u32 cs);
H A Dsdram_common.h419 u32 pctl_dis_zqcs_aref(void __iomem *pctl_base);
420 void pctl_rest_zqcs_aref(void __iomem *pctl_base, u32 dis_auto_zq);
421 void send_a_refresh(void __iomem *pctl_base, u32 cs);
433 int sdram_detect_bank(struct sdram_cap_info *cap_info, void __iomem *pctl_base,
435 int sdram_detect_bg(struct sdram_cap_info *cap_info, void __iomem *pctl_base,