503 	void __iomem *pctl_base = dram->pctl;  in sw_set_req()  local
506 	writel(PCTL2_SW_DONE_CLEAR, pctl_base + DDR_PCTL2_SWCTL);  in sw_set_req()
511 	void __iomem *pctl_base = dram->pctl;  in sw_set_ack()  local
514 	writel(PCTL2_SW_DONE, pctl_base + DDR_PCTL2_SWCTL);  in sw_set_ack()
517 		if (readl(pctl_base + DDR_PCTL2_SWSTAT) &  in sw_set_ack()
527 	void __iomem *pctl_base = dram->pctl;  in set_ctl_address_map()  local
546 	sdram_copy_to_reg((u32 *)(pctl_base + DDR_PCTL2_ADDRMAP0),  in set_ctl_address_map()
551 		setbits_le32(pctl_base + DDR_PCTL2_ADDRMAP6 +  in set_ctl_address_map()
556 		setbits_le32(pctl_base + DDR_PCTL2_ADDRMAP6, 1 << 31);  in set_ctl_address_map()
558 		setbits_le32(pctl_base + DDR_PCTL2_PCCFG, 1 << 8);  in set_ctl_address_map()
561 		clrsetbits_le32(pctl_base + DDR_PCTL2_ADDRMAP0, 0x1f, 0x1f);  in set_ctl_address_map()
815 	void __iomem *pctl_base = dram->pctl;  in set_lp4_vref()  local
871 	clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in set_lp4_vref()
876 	clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in set_lp4_vref()
887 	void __iomem *pctl_base = dram->pctl;  in set_ds_odt()  local
1093 		mr1_mr3 = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in set_ds_odt()
1097 		mr1_mr3 = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in set_ds_odt()
1165 		mr11 = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in set_ds_odt()
1177 		clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in set_ds_odt()
1184 		mr22 = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in set_ds_odt()
1200 		clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in set_ds_odt()
1209 		clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in set_ds_odt()
1216 		clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in set_ds_odt()
1302 	void __iomem *pctl_base = dram->pctl;  in update_refresh_reg()  local
1305 	ret = readl(pctl_base + DDR_PCTL2_RFSHCTL3) ^ (1 << 1);  in update_refresh_reg()
1306 	writel(ret, pctl_base + DDR_PCTL2_RFSHCTL3);  in update_refresh_reg()
1319 	void __iomem *pctl_base = dram->pctl;  in read_mr()  local
1323 	pctl_read_mr(pctl_base, rank, mr_num);  in read_mr()
1348 	void __iomem *pctl_base = dram->pctl;  in enter_sr()  local
1351 		setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, PCTL2_SELFREF_SW);  in enter_sr()
1353 			if (((readl(pctl_base + DDR_PCTL2_STAT) &  in enter_sr()
1356 			    ((readl(pctl_base + DDR_PCTL2_STAT) &  in enter_sr()
1362 		clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, PCTL2_SELFREF_SW);  in enter_sr()
1363 		while ((readl(pctl_base + DDR_PCTL2_STAT) &  in enter_sr()
1512 	void __iomem *pctl_base = dram->pctl;  in low_power_update()  local
1516 		setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, en & 0xf);  in low_power_update()
1518 		lp_stat = readl(pctl_base + DDR_PCTL2_PWRCTL) & 0xf;  in low_power_update()
1519 		clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 0xf);  in low_power_update()
1580 	void __iomem *pctl_base = dram->pctl;  in data_training_rg()  local
1604 		mr4_d4 = readl(pctl_base + DDR_PCTL2_INIT6) >> PCTL2_DDR4_MR4_SHIFT & PCTL2_MR_MASK;  in data_training_rg()
1606 		pctl_write_mr(pctl_base, BIT(cs), 4, mr4_d4 | BIT(11), DDR4);  in data_training_rg()
1623 		pctl_write_mr(pctl_base, BIT(cs), 4, mr4_d4, DDR4);  in data_training_rg()
1642 	void __iomem *pctl_base = dram->pctl;  in data_training_wl()  local
1653 	cur_fsp = readl(pctl_base + DDR_PCTL2_MSTR2) & 0x3;  in data_training_wl()
1654 	tmp = readl(pctl_base + UMCTL2_REGS_FREQ(cur_fsp) + DDR_PCTL2_INIT3) &  in data_training_wl()
1712 	void __iomem *pctl_base = dram->pctl;  in data_training_rd()  local
1745 	cur_fsp = readl(pctl_base + DDR_PCTL2_MSTR2) & 0x3;  in data_training_rd()
1747 	trefi_1x = ((readl(pctl_base + UMCTL2_REGS_FREQ(cur_fsp) +  in data_training_rd()
1749 	trfc_1x = readl(pctl_base + UMCTL2_REGS_FREQ(cur_fsp) +  in data_training_rd()
1829 	void __iomem *pctl_base = dram->pctl;  in data_training_wr()  local
1865 	cur_fsp = readl(pctl_base + DDR_PCTL2_MSTR2) & 0x3;  in data_training_wr()
1866 	trefi_1x = ((readl(pctl_base + UMCTL2_REGS_FREQ(cur_fsp) +  in data_training_wr()
1868 	trfc_1x = readl(pctl_base + UMCTL2_REGS_FREQ(cur_fsp) +  in data_training_wr()
1930 		mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(cur_fsp) +  in data_training_wr()
2222 	void __iomem *pctl_base = dram->pctl;  in update_noc_timing()  local
2226 	bl = ((readl(pctl_base + DDR_PCTL2_MSTR) >> 16) & 0xf) * 2;  in update_noc_timing()
2332 	void __iomem *pctl_base = dram->pctl;  in dram_all_config()  local
2348 		cs_pst = (readl(pctl_base + DDR_PCTL2_ADDRMAP0) & 0x1f) +  in dram_all_config()
2363 	void __iomem *pctl_base = dram->pctl;  in enable_low_power()  local
2381 		clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 1));  in enable_low_power()
2383 		setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 1));  in enable_low_power()
2385 		clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 1);  in enable_low_power()
2387 		setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 1);  in enable_low_power()
2388 	setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 3));  in enable_low_power()
2396 	void __iomem *pctl_base = dram->pctl;  in ddr_set_atags()  local
2432 		cs_pst = (readl(pctl_base + DDR_PCTL2_ADDRMAP0) & 0x1f) +  in ddr_set_atags()
2569 	void __iomem *pctl_base = dram->pctl;  in sdram_init_()  local
2592 		setbits_le32(pctl_base + DDR_PCTL2_SCHED, 1 << 2);  in sdram_init_()
2594 		clrsetbits_le32(pctl_base + DDR_PCTL2_SCHED1, 0xff, 0x1 << 0);  in sdram_init_()
2596 		clrbits_le32(pctl_base + DDR_PCTL2_SCHED, 1 << 2);  in sdram_init_()
2602 	tmp = readl(pctl_base + DDR_PCTL2_RFSHTMG);  in sdram_init_()
2605 	       pctl_base + DDR_PCTL2_RFSHTMG);  in sdram_init_()
2609 	setbits_le32(pctl_base + DDR_PCTL2_MSTR, 0x1 << 29);  in sdram_init_()
2611 	clrsetbits_le32(pctl_base + DDR_PCTL2_MSTR2, 0x3, 0);  in sdram_init_()
2617 	setbits_le32(pctl_base + DDR_PCTL2_DFIMISC, (1 << 5) | (1 << 4));  in sdram_init_()
2621 	while ((readl(pctl_base + DDR_PCTL2_STAT) & 0x7) == 0) {  in sdram_init_()
2634 		mr_tmp = readl(pctl_base + DDR_PCTL2_INIT6);  in sdram_init_()
2644 		mr_tmp = readl(pctl_base + DDR_PCTL2_INIT7);  in sdram_init_()
2650 		mr_tmp = readl(pctl_base + DDR_PCTL2_INIT7) >> PCTL2_DDR4_MR6_SHIFT & PCTL2_MR_MASK;  in sdram_init_()
2683 		mr_tmp = readl(pctl_base + DDR_PCTL2_INIT7);  in sdram_init_()
2714 	void __iomem *pctl_base = dram->pctl;  in dram_detect_cap()  local
2742 			sdram_detect_bank(cap_info, pctl_base, coltmp, bktmp);  in dram_detect_cap()
2752 			sdram_detect_bg(cap_info, pctl_base, coltmp);  in dram_detect_cap()
2785 	pwrctl = readl(pctl_base + DDR_PCTL2_PWRCTL);  in dram_detect_cap()
2786 	writel(0, pctl_base + DDR_PCTL2_PWRCTL);  in dram_detect_cap()
2816 	writel(pwrctl, pctl_base + DDR_PCTL2_PWRCTL);  in dram_detect_cap()
2840 	void __iomem *pctl_base = dram->pctl;  in dram_detect_cs1_row()  local
2851 		cs_pst = (readl(pctl_base + DDR_PCTL2_ADDRMAP0) & 0x1f) +  in dram_detect_cs1_row()
3015 	void __iomem *pctl_base = dram->pctl;  in pre_set_rate()  local
3029 				       pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in pre_set_rate()
3040 	tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + DDR_PCTL2_RFSHTMG);  in pre_set_rate()
3043 	       pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + DDR_PCTL2_RFSHTMG);  in pre_set_rate()
3070 		mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in pre_set_rate()
3089 		mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in pre_set_rate()
3104 		mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in pre_set_rate()
3117 		mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in pre_set_rate()
3139 	void __iomem *pctl_base = dram->pctl;  in save_fsp_param()  local
3173 		temp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in save_fsp_param()
3180 		temp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in save_fsp_param()
3187 		temp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in save_fsp_param()
3196 		temp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in save_fsp_param()
3201 		temp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in save_fsp_param()
3390 	void __iomem *pctl_base = dram->pctl;  in ddr_set_rate()  local
3403 	while ((readl(pctl_base + DDR_PCTL2_STAT) &  in ddr_set_rate()
3409 	dst_init3 = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in ddr_set_rate()
3415 	cur_fsp = readl(pctl_base + DDR_PCTL2_MSTR2) & 0x3;  in ddr_set_rate()
3416 	cur_init3 = readl(pctl_base + UMCTL2_REGS_FREQ(cur_fsp) +  in ddr_set_rate()
3432 	setbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3,  in ddr_set_rate()
3442 	clrbits_le32(pctl_base + DDR_PCTL2_DFIMISC,  in ddr_set_rate()
3448 		setbits_le32(pctl_base + DDR_PCTL2_MSTR, PCTL2_DLL_OFF_MODE);  in ddr_set_rate()
3450 		clrbits_le32(pctl_base + DDR_PCTL2_MSTR, PCTL2_DLL_OFF_MODE);  in ddr_set_rate()
3452 	setbits_le32(pctl_base + UMCTL2_REGS_FREQ(cur_fsp) + DDR_PCTL2_ZQCTL0,  in ddr_set_rate()
3454 	setbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + DDR_PCTL2_ZQCTL0,  in ddr_set_rate()
3480 	while ((readl(pctl_base + DDR_PCTL2_DFISTAT) &  in ddr_set_rate()
3491 	setbits_le32(pctl_base + DDR_PCTL2_MSTR, 0x1 << 29);  in ddr_set_rate()
3492 	clrsetbits_le32(pctl_base + DDR_PCTL2_MSTR2, 0x3, dst_fsp);  in ddr_set_rate()
3502 	mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + DDR_PCTL2_INIT4);  in ddr_set_rate()
3535 			mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in ddr_set_rate()
3546 			mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in ddr_set_rate()
3566 	clrbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3,  in ddr_set_rate()