16 void pctl_read_mr(void __iomem *pctl_base, u32 rank, u32 mr_num)  in pctl_read_mr()  argument
18 	writel((rank << 4) | (1 << 0), pctl_base + DDR_PCTL2_MRCTRL0);  in pctl_read_mr()
19 	writel((mr_num << 8), pctl_base + DDR_PCTL2_MRCTRL1);  in pctl_read_mr()
20 	setbits_le32(pctl_base + DDR_PCTL2_MRCTRL0, 1u << 31);  in pctl_read_mr()
21 	while (readl(pctl_base + DDR_PCTL2_MRCTRL0) & (1u << 31))  in pctl_read_mr()
23 	while (readl(pctl_base + DDR_PCTL2_MRSTAT) & PCTL2_MR_WR_BUSY)  in pctl_read_mr()
32 int pctl_write_mr(void __iomem *pctl_base, u32 rank, u32 mr_num, u32 arg,  in pctl_write_mr()  argument
35 	while (readl(pctl_base + DDR_PCTL2_MRSTAT) & PCTL2_MR_WR_BUSY)  in pctl_write_mr()
39 		       pctl_base + DDR_PCTL2_MRCTRL0);  in pctl_write_mr()
40 		writel(arg, pctl_base + DDR_PCTL2_MRCTRL1);  in pctl_write_mr()
43 		       pctl_base + DDR_PCTL2_MRCTRL0);  in pctl_write_mr()
45 		       pctl_base + DDR_PCTL2_MRCTRL1);  in pctl_write_mr()
48 	setbits_le32(pctl_base + DDR_PCTL2_MRCTRL0, 1u << 31);  in pctl_write_mr()
49 	while (readl(pctl_base + DDR_PCTL2_MRCTRL0) & (1u << 31))  in pctl_write_mr()
51 	while (readl(pctl_base + DDR_PCTL2_MRSTAT) & PCTL2_MR_WR_BUSY)  in pctl_write_mr()
61 int pctl_write_vrefdq(void __iomem *pctl_base, u32 rank, u32 vrefrate,  in pctl_write_vrefdq()  argument
70 	tccd_l = (readl(pctl_base + DDR_PCTL2_DRAMTMG4) >> 16) & 0xf;  in pctl_write_vrefdq()
81 	dis_auto_zq = pctl_dis_zqcs_aref(pctl_base);  in pctl_write_vrefdq()
84 	pctl_write_mr(pctl_base, rank, 6, value | (1 << 7), dramtype);  in pctl_write_vrefdq()
87 	pctl_write_mr(pctl_base, rank, 6, value | (1 << 7), dramtype);  in pctl_write_vrefdq()
89 	pctl_write_mr(pctl_base, rank, 6, value | (0 << 7), dramtype);  in pctl_write_vrefdq()
92 	pctl_rest_zqcs_aref(pctl_base, dis_auto_zq);  in pctl_write_vrefdq()
97 static int upctl2_update_ref_reg(void __iomem *pctl_base)  in upctl2_update_ref_reg()  argument
101 	ret = readl(pctl_base + DDR_PCTL2_RFSHCTL3) ^ (1 << 1);  in upctl2_update_ref_reg()
102 	writel(ret, pctl_base + DDR_PCTL2_RFSHCTL3);  in upctl2_update_ref_reg()
107 u32 pctl_dis_zqcs_aref(void __iomem *pctl_base)  in pctl_dis_zqcs_aref()  argument
112 	if (!(readl(pctl_base + DDR_PCTL2_ZQCTL0) &  in pctl_dis_zqcs_aref()
115 		setbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1 << 31);  in pctl_dis_zqcs_aref()
119 	setbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, 1);  in pctl_dis_zqcs_aref()
121 	upctl2_update_ref_reg(pctl_base);  in pctl_dis_zqcs_aref()
126 void pctl_rest_zqcs_aref(void __iomem *pctl_base, u32 dis_auto_zq)  in pctl_rest_zqcs_aref()  argument
130 		clrbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1 << 31);  in pctl_rest_zqcs_aref()
133 	clrbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, 1);  in pctl_rest_zqcs_aref()
135 	upctl2_update_ref_reg(pctl_base);  in pctl_rest_zqcs_aref()
142 void send_a_refresh(void __iomem *pctl_base, u32 rank)  in send_a_refresh()  argument
144 	while (readl(pctl_base + DDR_PCTL2_DBGSTAT) & rank)  in send_a_refresh()
146 	writel(rank, pctl_base + DDR_PCTL2_DBGCMD);  in send_a_refresh()
148 	while (readl(pctl_base + DDR_PCTL2_DBGSTAT) & rank)  in send_a_refresh()
190 int pctl_cfg(void __iomem *pctl_base, struct ddr_pctl_regs *pctl_regs,  in pctl_cfg()  argument
197 		       pctl_base + pctl_regs->pctl[i][0]);  in pctl_cfg()
199 	clrsetbits_le32(pctl_base + DDR_PCTL2_PWRTMG,  in pctl_cfg()
203 	clrsetbits_le32(pctl_base + DDR_PCTL2_HWLPCTL,  in pctl_cfg()
207 	setbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1u << 31);  in pctl_cfg()