| /rk3399_rockchip-uboot/drivers/ram/rockchip/ |
| H A D | sdram_rk3328.c | 30 struct msch_regs *msch; member
284 writel(ddrconfig, &dram->msch->ddrconf); in set_ddrconfig()
287 static void sdram_msch_config(struct msch_regs *msch, in sdram_msch_config() argument
290 writel(noc_timings->ddrtiming.d32, &msch->ddrtiming); in sdram_msch_config()
292 writel(noc_timings->ddrmode.d32, &msch->ddrmode); in sdram_msch_config()
293 writel(noc_timings->readlatency, &msch->readlatency); in sdram_msch_config()
295 writel(noc_timings->activate.d32, &msch->activate); in sdram_msch_config()
296 writel(noc_timings->devtodev.d32, &msch->devtodev); in sdram_msch_config()
297 writel(noc_timings->ddr4timing.d32, &msch->ddr4_timing); in sdram_msch_config()
298 writel(noc_timings->agingx0, &msch->aging0); in sdram_msch_config()
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| H A D | sdram_px30.c | 36 struct msch_regs *msch; member
304 writel(ddrconfig | (ddrconfig << 8), &dram->msch->deviceconf); in set_ddrconfig()
308 static void sdram_msch_config(struct msch_regs *msch, in sdram_msch_config() argument
319 &msch->devicesize); in sdram_msch_config()
322 &msch->ddrtiminga0); in sdram_msch_config()
324 &msch->ddrtimingb0); in sdram_msch_config()
326 &msch->ddrtimingc0); in sdram_msch_config()
328 &msch->devtodev0); in sdram_msch_config()
329 writel(noc_timings->ddrmode.d32, &msch->ddrmode); in sdram_msch_config()
331 &msch->ddr4timing); in sdram_msch_config()
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| H A D | dmc-rk3368.c | 33 struct rk3368_msch *msch; member
607 struct rk3368_msch *msch = priv->msch; in sdram_col_row_detect() local
613 writel(6, &msch->ddrconf); in sdram_col_row_detect()
633 writel(15, &msch->ddrconf); in sdram_col_row_detect()
661 static int msch_biu_config(struct rk3368_msch *msch, in msch_biu_config() argument
762 writel(i, &msch->ddrconf); in msch_biu_config()
805 struct rk3368_msch *msch = priv->msch; in setup_sdram() local
817 writel(0x32, &msch->readlatency); in setup_sdram()
865 ret = msch_biu_config(msch, params); in setup_sdram()
917 struct rk3368_msch *msch; in rk3368_dmc_probe() local
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| H A D | sdram_rk3288.c | 35 struct rk3288_msch *msch; member
296 struct rk3288_msch *msch = chan->msch; in phy_cfg() local
305 writel(sdram_params->base.noc_timing, &msch->ddrtiming); in phy_cfg()
306 writel(0x3f, &msch->readlatency); in phy_cfg()
307 writel(sdram_params->base.noc_activate, &msch->activate); in phy_cfg()
309 1 << BUSRDTORD_SHIFT, &msch->devtodev); in phy_cfg()
442 struct rk3288_msch *msch = chan->msch; in set_bandwidth_ratio() local
447 setbits_le32(&msch->ddrtiming, 1 << 31); in set_bandwidth_ratio()
457 clrbits_le32(&msch->ddrtiming, 1 << 31); in set_bandwidth_ratio()
589 writel(sdram_params->base.ddrconfig, &chan->msch->ddrconf); in dram_cfg_rbc()
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| H A D | sdram_rk3188.c | 33 struct rk3188_msch *msch; member
262 struct rk3188_msch *msch = chan->msch; in phy_cfg() local
271 writel(sdram_params->base.noc_timing, &msch->ddrtiming); in phy_cfg()
272 writel(0x3f, &msch->readlatency); in phy_cfg()
384 struct rk3188_msch *msch = chan->msch; in set_bandwidth_ratio() local
389 setbits_le32(&msch->ddrtiming, 1 << 31); in set_bandwidth_ratio()
399 clrbits_le32(&msch->ddrtiming, 1 << 31); in set_bandwidth_ratio()
532 writel(sdram_params->base.ddrconfig, &chan->msch->ddrconf); in dram_cfg_rbc()
658 writel(1, &chan->msch->ddrconf); in sdram_col_row_detect()
776 writel(1, &chan->msch->ddrconf); in sdram_init()
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| H A D | sdram_rk3399.c | 33 struct msch_regs *msch; member
1777 struct msch_regs *ddr_msch_regs = chan->msch; in set_ddrconfig()
1798 static void sdram_msch_config(struct msch_regs *msch, in sdram_msch_config() argument
1802 &msch->ddrtiminga0.d32); in sdram_msch_config()
1804 &msch->ddrtimingb0.d32); in sdram_msch_config()
1806 &msch->ddrtimingc0.d32); in sdram_msch_config()
1808 &msch->devtodev0.d32); in sdram_msch_config()
1810 &msch->ddrmode.d32); in sdram_msch_config()
1832 ddr_msch_regs = dram->chan[channel].msch; in dram_all_config()
2165 struct msch_regs *ddr_msch_regs = chan->msch; in dram_set_cs()
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| H A D | sdram_rk322x.c | 29 struct rk322x_service_sys *msch; member
472 struct rk322x_service_sys *axi_bus = chan->msch; in phy_cfg()
537 struct rk322x_service_sys *axi_bus = chan->msch; in dram_cfg_rbc()
605 struct rk322x_service_sys *axi_bus = dram->chan[0].msch; in dram_cap_detect()
794 priv->chan[0].msch = syscon_get_first_range(ROCKCHIP_SYSCON_MSCH); in rk322x_dmc_probe()
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| H A D | sdram_rv1126.c | 53 struct msch_regs *msch; member
2215 writel(ddrconfig, &dram->msch->deviceconf); in set_ddrconfig()
2250 &dram->msch->ddrtiminga0); in update_noc_timing()
2252 &dram->msch->ddrtimingb0); in update_noc_timing()
2254 &dram->msch->ddrtimingc0); in update_noc_timing()
2256 &dram->msch->devtodev0); in update_noc_timing()
2257 writel(sdram_params->ch.noc_timings.ddrmode.d32, &dram->msch->ddrmode); in update_noc_timing()
2259 &dram->msch->ddr4timing); in update_noc_timing()
2356 &dram->msch->devicesize); in dram_all_config()
3659 dram_info.msch = (void *)SERVER_MSCH_BASE_ADDR; in sdram_init()
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| /rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3066/ |
| H A D | sdram_rk3066.c | 33 struct rk3188_msch *msch; member
251 struct rk3188_msch *msch = chan->msch; in phy_cfg() local
260 writel(sdram_params->base.noc_timing, &msch->ddrtiming); in phy_cfg()
261 writel(0x3f, &msch->readlatency); in phy_cfg()
373 struct rk3188_msch *msch = chan->msch; in set_bandwidth_ratio() local
377 setbits_le32(&msch->ddrtiming, 1 << 31); in set_bandwidth_ratio()
386 clrbits_le32(&msch->ddrtiming, 1 << 31); in set_bandwidth_ratio()
519 writel(sdram_params->base.ddrconfig, &chan->msch->ddrconf); in dram_cfg_rbc()
645 writel(1, &chan->msch->ddrconf); in sdram_col_row_detect()
756 writel(1, &chan->msch->ddrconf); in sdram_init()
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| /rk3399_rockchip-uboot/arch/arm/dts/ |
| H A D | rk322x.dtsi | 858 rockchip,msch = <&service_msch>;
865 compatible = "rockchip,rk3228-msch", "syscon";
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| H A D | rk3128.dtsi | 142 msch {
147 msch@10128000 {
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| H A D | rk3368.dtsi | 235 rockchip,msch = <&service_msch>;
241 compatible = "rockchip,rk3368-msch", "syscon";
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