rockchip: dts: enable psci node

In order to bind psci-sysreset driver if no kernel dtb.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I93c3d08b6113ba9d7c49a4500c69854879554b5b

Merge branch 'next-dev' into thunder-boot

rockchip: dts: rk3368: add and enable crypto node

Change-Id: Icfffb1311388ff7de59b9c9da7d5f25c7eb35684
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>

rockchip: dts: rk3368: add cd-gpios

Add cd-gpios to test the mmc device whether exit.

Change-Id: I8ab96fd5300da25d82005ac638e6d2b728ed82ce
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>

rockchip: dts: rk3368: enable nandc

fix model string typo.

Change-Id: I1e96a986a381c86999839efd486fb371ca8ed82c
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

rockchip: dts: rk3368: add usb host/phy nodes

Change-Id: I8f7e33d204c63f5455dd33e5b254998e6f20d0da
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

rockchip: dts: update mmc property "ciu-sample"

dts property always use '-' instead of '_' for description

Change-Id: I216549bec2850c614b2173ac4a3bae58da317379
Signed-off-by: Kever Yang <kever.yang

rockchip: dts: update mmc property "ciu-sample"

dts property always use '-' instead of '_' for description

Change-Id: I216549bec2850c614b2173ac4a3bae58da317379
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

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pwm: rockchip: Do pwm pinctrl setting after pwm enabled

If the PWM pinctrl uses default state, the iomux setting will
be done at probe, the PWM may not be enabled at this moment.
It will make PWM in

pwm: rockchip: Do pwm pinctrl setting after pwm enabled

If the PWM pinctrl uses default state, the iomux setting will
be done at probe, the PWM may not be enabled at this moment.
It will make PWM into an intermediate state, destroy the default
hardware state, the PWM is not ready for work yet. So it is better
for doing PWM pinctrl setting after PWM enabled.

Change-Id: I8b700a07083b9a6798303fc5a5ed9f29eb42c47e
Signed-off-by: David Wu <david.wu@rock-chips.com>

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Merge branch 'master' of git://git.denx.de/u-boot-rockchip

dts: rk3368: make timer0 accessible for SPL and TPL

To use it with the DM timer driver in SPL and TPL, timer0 needs to be
marked as pre-reloc.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobr

dts: rk3368: make timer0 accessible for SPL and TPL

To use it with the DM timer driver in SPL and TPL, timer0 needs to be
marked as pre-reloc.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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rockchip: board: lion-rk3368: add support for the RK3368-uQ7

The RK3368-uQ7 (codenamed 'Lion') is a micro-Qseven (40mm x 70mm,
MXM-230 edge connector compatible with the Qseven specification)
form-f

rockchip: board: lion-rk3368: add support for the RK3368-uQ7

The RK3368-uQ7 (codenamed 'Lion') is a micro-Qseven (40mm x 70mm,
MXM-230 edge connector compatible with the Qseven specification)
form-factor system-on-module based on the octo-core Rockchip RK3368.
It is designed, supported and manufactured by Theobroma Systems.

It provides the following features:
- 8x Cortex-A53 (in 2 clusters of 4 cores each)
- (on-module) up to 4GB of DDR3 memory
- (on-module) SPI-NOR flash
- (on-module) eMMC
- Gigabit Ethernet (with an on-module KSZ9031 PHY)
- USB
- HDMI
- MIPI-DSI/single-channel LVDS (muxed on the 'LVDS-A' pin-group)
- various 'slow' interfaces (e.g. UART, SPI, I2C, I2S, ...)

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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rockchip: rk3368: dts: add DMC node in rk3368.dtsi

For full SPL support, including DRAM initialisation, we need a few
nodes from the DTS: this commit adds the DMC (DRAM controller) node,
the service

rockchip: rk3368: dts: add DMC node in rk3368.dtsi

For full SPL support, including DRAM initialisation, we need a few
nodes from the DTS: this commit adds the DMC (DRAM controller) node,
the service_msch (memory scheduler) node and marks GRF, PMUGRF and CRU
as 'u-boot,dm-pre-reloc'. In addition to this, we also include the
dt-binding for the DMC to allow DTS files including this DTSI to refer
to the symbolic constants for the DDR3 bin and for the
memory-schedule.

Note that the DMC contains both the memory regions for the
(Designware) protocol controller as well as the DDR PHY.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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rockchip: rk3368: dts: add sgrf node

We will to drop device security temporarily (until the ATF initialises
it fully) from the TPL/SPL stage: this requires access to some
registers in the SGRF.

Thi

rockchip: rk3368: dts: add sgrf node

We will to drop device security temporarily (until the ATF initialises
it fully) from the TPL/SPL stage: this requires access to some
registers in the SGRF.

This adds the sgrf node to the rk3368.dtsi, so we can then bind a
syscon device onto it and access its memory ranges.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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Merge branch 'master' of git://git.denx.de/u-boot-rockchip

rockchip: dts: rk3368: add dmc node

Add dmc node to enable sdram driver.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

Merge git://git.denx.de/u-boot-rockchip

Here is additional rk3368 and rk3399 support, rv1108 support,
refactoring HDMI video (brought in from Anatolij's tree to resolve
conflicts), some mkimage fixe

Merge git://git.denx.de/u-boot-rockchip

Here is additional rk3368 and rk3399 support, rv1108 support,
refactoring HDMI video (brought in from Anatolij's tree to resolve
conflicts), some mkimage fixes and a few other things.

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rockchip: rk3368: Add core start-up code for RK3368

The RK3368 is an octa-core Cortex-A53 SoC from Rockchip.
This adds basic support to chain-load U-Boot from Rockchip's
miniloader.

Signed-off-by:

rockchip: rk3368: Add core start-up code for RK3368

The RK3368 is an octa-core Cortex-A53 SoC from Rockchip.
This adds basic support to chain-load U-Boot from Rockchip's
miniloader.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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