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Searched refs:mrc (Results 1 – 25 of 47) sorted by relevance

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/rk3399_rockchip-uboot/arch/arm/include/asm/
H A Darm32_macros.S9 mrc p15, 0, \reg, c0, c0, 0
13 mrc p15, 0, \reg, c0, c0, 1
17 mrc p15, 0, \reg, c0, c0, 5
21 mrc p15, 0, \reg, c1, c0, 0
33 mrc p15, 0, \reg, c1, c0, 1
41 mrc p15, 0, \reg, c1, c0, 2
45 mrc p15, 0, \reg, c1, c1, 0
57 mrc p15, 0, \reg, c1, c1, 2
65 mrc p15, 0, \reg, c2, c0, 0
73 mrc p15, 0, \reg, c2, c0, 1
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/
H A Dstart.S49 mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
68 mrc p15, 0, r0, c1, c0, 1
79 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTLR Register
164 mrc p15, 0, r0, c1, c0, 0
179 mrc p15, 0, r0, c1, c0, 0 @ read system control register
185 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
191 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
197 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
202 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
208 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
[all …]
H A Dnonsec_virt.S33 mrc p15, 0, \tmp, c0, c1, 1 @ read ID_PFR1
62 mrc p15, 0, r5, c1, c0, 1
69 mrc p15, 0, r5, c1, c0, 1
75 mrc p15, 0, r5, c1, c1, 0 @ read SCR
92 mrc p15, 0, r4, c0, c1, 1 @ read ID_PFR1
117 mrc p15, 4, \addr, c15, c0, 0 @ read CBAR
179 mrc p15, 0, r0, c1, c1, 2
192 mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
H A Dpsci.S158 mrc p15, 0, r7, c1, c1, 0
183 mrc p15, 0, r0, c0, c0, 5 /* read MPIDR */
193 mrc p15, 1, r0, c0, c0, 1 @ read clidr
207 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
243 mrc p15, 0, r0, c1, c0, 1 @ ACTLR
253 mrc p15, 0, r0, c1, c0, 1 @ ACTLR
268 mrc p15, 0, r0, c1, c0, 0 @ SCTLR
/rk3399_rockchip-uboot/arch/arm/mach-rmobile/
H A Dlowlevel_init_ca15.S14 mrc p15, 0, r4, c0, c0, 5 /* mpidr */
52 mrc p15, 0, r0, c0, c0, 5 /* r0 = MPIDR */
58 mrc p15, 1, r0, c9, c0, 2 /* r0 = L2CTLR */
72 mrc p15, 0, r0, c1, c0, 1
/rk3399_rockchip-uboot/doc/device-tree-bindings/misc/
H A Dintel,baytrail-fsp.txt34 - fsp,mrc-debug-msg
51 - fsp,mrc-init-tseg-size
52 - fsp,mrc-init-mmio-size
53 - fsp,mrc-init-spd-addr1
54 - fsp,mrc-init-spd-addr2
102 fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
103 fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
104 fsp,mrc-init-spd-addr1 = <0xa0>;
105 fsp,mrc-init-spd-addr2 = <0xa2>;
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/sunxi/
H A Dfel_utils.S20 mrc p15, 0, lr, c1, c0, 0 @ Read CP15 SCTLR Register
22 mrc p15, 0, lr, c12, c0, 0 @ Read VBAR
24 mrc p15, 0, lr, c1, c0, 0 @ Read CP15 Control Register
/rk3399_rockchip-uboot/arch/x86/dts/
H A Dgalileo.dts9 #include <dt-bindings/mrc/quark.h>
48 mrc {
49 compatible = "intel,quark-mrc";
144 rw-mrc-cache {
145 label = "rw-mrc-cache";
H A Dbaytrail_som-db5800-som-6867.dts204 rw-mrc-cache {
205 label = "rw-mrc-cache";
263 fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
264 fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
265 fsp,mrc-init-spd-addr1 = <0xa0>;
266 fsp,mrc-init-spd-addr2 = <0xa2>;
H A Dbayleybay.dts181 rw-mrc-cache {
182 label = "rw-mrc-cache";
240 fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
241 fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
242 fsp,mrc-init-spd-addr1 = <0xa0>;
243 fsp,mrc-init-spd-addr2 = <0xa2>;
H A Dchromebox_panther.dts52 rw-mrc-cache {
53 label = "rw-mrc-cache";
H A Dconga-qeval20-qa3-e3845.dts191 rw-mrc-cache {
192 label = "rw-mrc-cache";
250 fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
251 fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
252 fsp,mrc-init-spd-addr1 = <0xa0>;
253 fsp,mrc-init-spd-addr2 = <0xa2>;
H A Ddfi-bt700.dtsi202 rw-mrc-cache {
203 label = "rw-mrc-cache";
261 fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
262 fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
263 fsp,mrc-init-spd-addr1 = <0xa0>;
264 fsp,mrc-init-spd-addr2 = <0xa2>;
H A Dminnowmax.dts205 rw-mrc-cache {
206 label = "rw-mrc-cache";
264 fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
265 fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
266 fsp,mrc-init-spd-addr1 = <0xa0>;
267 fsp,mrc-init-spd-addr2 = <0xa2>;
/rk3399_rockchip-uboot/arch/arm/mach-uniphier/arm32/
H A Dpsci_smp.S15 mrc p15, 0, r1, c1, c0, 0 @ SCTLR (System Control Register)
27 mrc p15, 0, r1, c0, c0, 5 @ MPIDR (Multiprocessor Affinity Reg)
H A Dlowlevel_init.S24 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
43 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
54 mrc p15, 0, r0, c2, c0, 2 @ TTBCR (Translation Table Base Control Register)
75 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
/rk3399_rockchip-uboot/arch/arm/cpu/arm926ejs/
H A Dstart.S80 mrc p15, 0, r15, c7, c10, 3
90 mrc p15, 0, r0, c1, c0, 0
/rk3399_rockchip-uboot/arch/arm/cpu/pxa/
H A Dstart.S108 mrc p15, 0, r0, c1, c0, 0
125 mrc p15, 0, \reg, c2, c0, 0
139 mrc p15, 0, r0, c1, c0, 0
/rk3399_rockchip-uboot/arch/x86/cpu/quark/
H A DMakefile8 obj-y += mrc.o mrc_util.o hte.o smc.o
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-mx6/
H A Dmx6_plugin.S89 mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 into r0*/
94 mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 into r0 */
/rk3399_rockchip-uboot/arch/arm/mach-zynq/
H A Dlowlevel_init.S14 mrc p15, 0, r1, c1, c0, 2
/rk3399_rockchip-uboot/arch/x86/cpu/intel_common/
H A DMakefile11 obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += mrc.o
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-mx35/
H A Dlowlevel_macro.S99 mrc p15, 0, r1, c1, c0, 0
102 mrc p15, 0, r0, c1, c0, 1
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-armv7/
H A Dgenerictimer.h40 mrc p15, 0, \reg, c14, c2, 1
/rk3399_rockchip-uboot/arch/arm/cpu/arm926ejs/spear/
H A Dstart.S71 mrc p15, 0, r0, c1, c0, 0

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