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/rk3399_rockchip-uboot/doc/SPI/
H A DREADME.dual-flash7 Current spi_flash framework supports, single flash memory connected
17 - single spi flash memory connected with single chip select line.
21 | Controller | I0[3:0] | Flash memory |
35 | | +=========>| memory |
41 | |<===========+====|====>| memory |
46 - two memory flash devices should has same hw part attributes (like size,
50 Enable U_PAGE[BIT:28] if U_PAGE flag set - upper memory
51 Disable U_PAGE[BIT:28] if U_PAGE flag unset - lower memory
54 by default, if U_PAGE is unset lower memory should accessible,
55 once user wants to access upper memory need to set U_PAGE.
[all …]
/rk3399_rockchip-uboot/doc/device-tree-bindings/ram/
H A Dst,stm32-fmc.txt1 ST, stm32 flexible memory controller Drive
6 u-boot,dm-pre-reloc: flag to initialize memory before relocation.
8 on-board sdram memory attributes:
12 memory width
13 number of intenal banks in memory
27 include/dt-bindings/memory/stm32-sdram.h to define sdram control and timing
43 /* sdram memory configuration from sdram datasheet */
51 /* sdram memory configuration from sdram datasheet */
/rk3399_rockchip-uboot/doc/device-tree-bindings/clock/
H A Drockchip,rk3368-dmc.txt1 RK3368 dynamic memory controller driver
4 The RK3368 DMC (dynamic memory controller) driver supports setup/initialisation
7 (a) a target-frequency (i.e. operating point) for the memory operation
9 (c) a memory-schedule (i.e. mapping from physical addresses to the address
10 pins of the memory bus)
44 - rockchip,memory-schedule:
54 #include <dt-bindings/memory/rk3368-dmc.h>
66 rockchip,memory-schedule = <DMC_MSCH_CBRD>;
/rk3399_rockchip-uboot/doc/
H A DREADME.memory-test2 hardware, or when using a sloppy port on some board, is memory errors.
4 incorrect initialization of the memory controller. So it appears to
5 be a good idea to always test if the memory is working correctly,
8 U-Boot implements 3 different approaches to perform memory tests:
14 memory banks on this piece of hardware. The code is supposed to be
17 catch 99% of hardware related (i. e. reliably reproducible) memory
23 This is probably the best known memory test utility in U-Boot.
35 no knowledge about memory ranges that may be in use for other
46 system memory) and for U-Boot (code, data, etc. - see above;
47 these are usually at the very upper end of system memory). But
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H A DREADME.unaligned-memory-access.txt8 when it comes to memory access. This document presents some details about
16 Unaligned memory accesses occur when you try to read N bytes of data starting
19 reading 4 bytes of data from address 0x10005 would be an unaligned memory
22 The above may seem a little vague, as memory access can happen in different
24 or write a number of bytes to or from memory (e.g. movb, movw, movl in x86
26 which will compile to multiple-byte memory access instructions, namely when
34 When accessing N bytes of memory, the base memory address must be evenly
41 of memory access. However, we must consider ALL supported architectures;
49 The effects of performing an unaligned memory access vary from architecture
53 - Some architectures are able to perform unaligned memory accesses
[all …]
H A DREADME.mpc85xx-spin-table3 As specified by ePAPR v1.1, the spin table needs to be in cached memory. After
9 Core 0 sets up the reset page on the top 4K of memory (or 4GB if total memory
12 page translation for secondary cores to use this page of memory. Then 4KB
13 memory is copied from __secondary_start_page to the boot page, after flusing
16 relocated to the top of mapped memory) into a variable __spin_table_addr so
/rk3399_rockchip-uboot/arch/x86/dts/
H A Dskeleton.dtsi3 * add a compatible value. The bootloader will typically populate the memory
12 memory { device_type = "memory"; reg = <0 0>; };
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dskeleton.dtsi3 * add a compatible value. The bootloader will typically populate the memory
12 memory { device_type = "memory"; reg = <0 0>; };
H A Dskeleton64.dtsi4 * bootloader will typically populate the memory node.
12 memory { device_type = "memory"; reg = <0 0 0 0>; };
H A Dhi6220-hikey.dts10 /*Reserved 1MB memory for MCU*/
30 memory@0 {
31 device_type = "memory";
H A Dsocfpga_cyclone5_mcvevk.dts22 memory {
23 name = "memory";
24 device_type = "memory";
H A Dsocfpga_cyclone5_de1_soc.dts22 memory {
23 name = "memory";
24 device_type = "memory";
H A Dsocfpga_cyclone5_de0_nano_soc.dts22 memory {
23 name = "memory";
24 device_type = "memory";
H A Dsocfpga_cyclone5_de10_nano.dts24 memory {
25 name = "memory";
26 device_type = "memory";
H A Dfsl-ls2080a.dtsi15 memory@80000000 {
16 device_type = "memory";
75 reg-names = "QuadSPI", "QuadSPI-memory";
105 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
120 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
135 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
150 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
/rk3399_rockchip-uboot/arch/mips/dts/
H A Dskeleton.dtsi3 * add a compatible value. The bootloader will typically populate the memory
19 memory {
20 device_type = "memory";
/rk3399_rockchip-uboot/lib/
H A Dlmb.c21 debug(" memory.cnt = 0x%lx\n", lmb->memory.cnt); in lmb_dump_all()
23 (unsigned long long)lmb->memory.size); in lmb_dump_all()
24 for (i=0; i < lmb->memory.cnt ;i++) { in lmb_dump_all()
26 (long long unsigned)lmb->memory.region[i].base); in lmb_dump_all()
28 (long long unsigned)lmb->memory.region[i].size); in lmb_dump_all()
96 lmb->memory.region[0].base = 0; in lmb_init()
97 lmb->memory.region[0].size = 0; in lmb_init()
98 lmb->memory.cnt = 1; in lmb_init()
99 lmb->memory.size = 0; in lmb_init()
178 struct lmb_region *_rgn = &(lmb->memory); in lmb_add()
[all …]
/rk3399_rockchip-uboot/arch/arc/dts/
H A Dskeleton.dtsi3 * add a compatible value. The bootloader will typically populate the memory
26 memory@80000000 {
27 device_type = "memory";
/rk3399_rockchip-uboot/doc/device-tree-bindings/spi/
H A Dspi-stm32-qspi.txt16 - memory-map : Address and size for memory-mapping the flash
24 reg-names = "QuadSPI", "QuadSPI-memory";
36 memory-map = <0x90000000 0x1000000>;
/rk3399_rockchip-uboot/doc/device-tree-bindings/misc/
H A Dintel,baytrail-fsp.txt41 - fsp,enable-memory-down
43 If you set "fsp,enable-memory-down" you are strongly encouraged to provide an
44 "fsp,memory-down-params{};" to specify how your memory is configured. If you
45 do not set "fsp,enable-memory-down", then the DIMM SPD information will be
46 discovered by the FSP and used to setup main memory.
66 - fsp,memory-down-params {
134 fsp,enable-memory-down;
135 fsp,memory-down-params {
/rk3399_rockchip-uboot/doc/device-tree-bindings/mtd/spi/
H A Dspi-flash.txt14 - memory-map : Address and size of the flash, if memory mapped. This may
15 apply to Intel chipsets, which tend to memory-map flash.
/rk3399_rockchip-uboot/arch/xtensa/dts/
H A Dkc705.dts11 memory@0 {
12 device_type = "memory";
H A Dml605.dts11 memory@0 {
12 device_type = "memory";
H A Dkc705_nommu.dts10 memory@0 {
11 device_type = "memory";
H A Dml605_nommu.dts11 memory@0 {
12 device_type = "memory";

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