Searched refs:mctrl (Results 1 – 7 of 7) sorted by relevance
32 | WDTIM_MCTRL_M_RES2, &wdt->mctrl); in reset_cpu()38 writel(WDTIM_MCTRL_M_RES1, &wdt->mctrl); in reset_cpu()
29 writel(WDTIM_MCTRL_RESFRC1, &wdt->mctrl); in reset_periph()31 writel(0, &wdt->mctrl); in reset_periph()
27 writel(WDTIM_MCTRL_RESFRC1, &wdt->mctrl); in reset_periph()30 writel(0, &wdt->mctrl); in reset_periph()
17 u32 mctrl; /* Match Control Register */ member
45 return (readl(&devcfg_base->mctrl) & ZYNQ_SILICON_VER_MASK) in zynq_get_silicon_version()
111 u32 mctrl; /* 0x80 */ member
200 clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK); in zynq_dma_xfer_init()246 writel(DEVCFG_MCTRL_RFIFO_FLUSH, &devcfg_base->mctrl); in zynq_dma_xfer_init()