1*412ae53aSAlbert ARIBAUD \(3ADEV\) /*
2*412ae53aSAlbert ARIBAUD \(3ADEV\) * WORK Microwave work_92105 board support
3*412ae53aSAlbert ARIBAUD \(3ADEV\) *
4*412ae53aSAlbert ARIBAUD \(3ADEV\) * (C) Copyright 2014 DENX Software Engineering GmbH
5*412ae53aSAlbert ARIBAUD \(3ADEV\) * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
6*412ae53aSAlbert ARIBAUD \(3ADEV\) *
7*412ae53aSAlbert ARIBAUD \(3ADEV\) * SPDX-License-Identifier: GPL-2.0+
8*412ae53aSAlbert ARIBAUD \(3ADEV\) */
9*412ae53aSAlbert ARIBAUD \(3ADEV\)
10*412ae53aSAlbert ARIBAUD \(3ADEV\) #include <common.h>
11*412ae53aSAlbert ARIBAUD \(3ADEV\) #include <asm/io.h>
12*412ae53aSAlbert ARIBAUD \(3ADEV\) #include <asm/arch/sys_proto.h>
13*412ae53aSAlbert ARIBAUD \(3ADEV\) #include <asm/arch/cpu.h>
14*412ae53aSAlbert ARIBAUD \(3ADEV\) #include <asm/arch/clk.h>
15*412ae53aSAlbert ARIBAUD \(3ADEV\) #include <asm/arch/emc.h>
16*412ae53aSAlbert ARIBAUD \(3ADEV\) #include <asm/arch/wdt.h>
17*412ae53aSAlbert ARIBAUD \(3ADEV\) #include <asm/gpio.h>
18*412ae53aSAlbert ARIBAUD \(3ADEV\) #include <spl.h>
19*412ae53aSAlbert ARIBAUD \(3ADEV\) #include "work_92105_display.h"
20*412ae53aSAlbert ARIBAUD \(3ADEV\)
21*412ae53aSAlbert ARIBAUD \(3ADEV\) DECLARE_GLOBAL_DATA_PTR;
22*412ae53aSAlbert ARIBAUD \(3ADEV\)
23*412ae53aSAlbert ARIBAUD \(3ADEV\) static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
24*412ae53aSAlbert ARIBAUD \(3ADEV\) static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE;
25*412ae53aSAlbert ARIBAUD \(3ADEV\)
reset_periph(void)26*412ae53aSAlbert ARIBAUD \(3ADEV\) void reset_periph(void)
27*412ae53aSAlbert ARIBAUD \(3ADEV\) {
28*412ae53aSAlbert ARIBAUD \(3ADEV\) setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
29*412ae53aSAlbert ARIBAUD \(3ADEV\) writel(WDTIM_MCTRL_RESFRC1, &wdt->mctrl);
30*412ae53aSAlbert ARIBAUD \(3ADEV\) udelay(150);
31*412ae53aSAlbert ARIBAUD \(3ADEV\) writel(0, &wdt->mctrl);
32*412ae53aSAlbert ARIBAUD \(3ADEV\) clrbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
33*412ae53aSAlbert ARIBAUD \(3ADEV\) }
34*412ae53aSAlbert ARIBAUD \(3ADEV\)
board_early_init_f(void)35*412ae53aSAlbert ARIBAUD \(3ADEV\) int board_early_init_f(void)
36*412ae53aSAlbert ARIBAUD \(3ADEV\) {
37*412ae53aSAlbert ARIBAUD \(3ADEV\) /* initialize serial port for console */
38*412ae53aSAlbert ARIBAUD \(3ADEV\) lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
39*412ae53aSAlbert ARIBAUD \(3ADEV\) /* enable I2C, SSP, MAC, NAND */
40*412ae53aSAlbert ARIBAUD \(3ADEV\) lpc32xx_i2c_init(1); /* only I2C1 has devices, I2C2 has none */
41*412ae53aSAlbert ARIBAUD \(3ADEV\) lpc32xx_ssp_init();
42*412ae53aSAlbert ARIBAUD \(3ADEV\) lpc32xx_mac_init();
43*412ae53aSAlbert ARIBAUD \(3ADEV\) lpc32xx_mlc_nand_init();
44*412ae53aSAlbert ARIBAUD \(3ADEV\) /* Display must wait until after relocation and devices init */
45*412ae53aSAlbert ARIBAUD \(3ADEV\) return 0;
46*412ae53aSAlbert ARIBAUD \(3ADEV\) }
47*412ae53aSAlbert ARIBAUD \(3ADEV\)
48*412ae53aSAlbert ARIBAUD \(3ADEV\) #define GPO_19 115
49*412ae53aSAlbert ARIBAUD \(3ADEV\)
board_early_init_r(void)50*412ae53aSAlbert ARIBAUD \(3ADEV\) int board_early_init_r(void)
51*412ae53aSAlbert ARIBAUD \(3ADEV\) {
52*412ae53aSAlbert ARIBAUD \(3ADEV\) /* Set NAND !WP to 1 through GPO_19 */
53*412ae53aSAlbert ARIBAUD \(3ADEV\) gpio_request(GPO_19, "NAND_nWP");
54*412ae53aSAlbert ARIBAUD \(3ADEV\) gpio_direction_output(GPO_19, 1);
55*412ae53aSAlbert ARIBAUD \(3ADEV\)
56*412ae53aSAlbert ARIBAUD \(3ADEV\) /* initialize display */
57*412ae53aSAlbert ARIBAUD \(3ADEV\) work_92105_display_init();
58*412ae53aSAlbert ARIBAUD \(3ADEV\)
59*412ae53aSAlbert ARIBAUD \(3ADEV\) return 0;
60*412ae53aSAlbert ARIBAUD \(3ADEV\) }
61*412ae53aSAlbert ARIBAUD \(3ADEV\)
board_init(void)62*412ae53aSAlbert ARIBAUD \(3ADEV\) int board_init(void)
63*412ae53aSAlbert ARIBAUD \(3ADEV\) {
64*412ae53aSAlbert ARIBAUD \(3ADEV\) reset_periph();
65*412ae53aSAlbert ARIBAUD \(3ADEV\) /* adress of boot parameters */
66*412ae53aSAlbert ARIBAUD \(3ADEV\) gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
67*412ae53aSAlbert ARIBAUD \(3ADEV\)
68*412ae53aSAlbert ARIBAUD \(3ADEV\) return 0;
69*412ae53aSAlbert ARIBAUD \(3ADEV\) }
70*412ae53aSAlbert ARIBAUD \(3ADEV\)
dram_init(void)71*412ae53aSAlbert ARIBAUD \(3ADEV\) int dram_init(void)
72*412ae53aSAlbert ARIBAUD \(3ADEV\) {
73*412ae53aSAlbert ARIBAUD \(3ADEV\) gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
74*412ae53aSAlbert ARIBAUD \(3ADEV\) CONFIG_SYS_SDRAM_SIZE);
75*412ae53aSAlbert ARIBAUD \(3ADEV\)
76*412ae53aSAlbert ARIBAUD \(3ADEV\) return 0;
77*412ae53aSAlbert ARIBAUD \(3ADEV\) }
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