Home
last modified time | relevance | path

Searched refs:link_train (Results 1 – 5 of 5) sorted by relevance

/rk3399_rockchip-uboot/drivers/video/drm/
H A Danalogix_dp.c194 lane_count = dp->link_train.lane_count; in analogix_dp_link_start()
196 dp->link_train.lt_state = CLOCK_RECOVERY; in analogix_dp_link_start()
197 dp->link_train.eq_loop = 0; in analogix_dp_link_start()
200 dp->link_train.cr_loop[lane] = 0; in analogix_dp_link_start()
203 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate); in analogix_dp_link_start()
204 analogix_dp_set_lane_count(dp, dp->link_train.lane_count); in analogix_dp_link_start()
208 drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, dp->link_train.lane_count); in analogix_dp_link_start()
212 buf[0] = dp->link_train.link_rate; in analogix_dp_link_start()
213 buf[1] = dp->link_train.lane_count; in analogix_dp_link_start()
242 dp->link_train.training_lane[lane] = in analogix_dp_link_start()
[all …]
H A Danalogix_dp_reg.c712 return dp->plat_data.ssc && dp->link_train.ssc; in analogix_dp_ssc_supported()
723 phy_cfg.dp.lanes = dp->link_train.lane_count; in analogix_dp_set_link_bandwidth()
725 drm_dp_bw_code_to_link_rate(dp->link_train.link_rate) / 100; in analogix_dp_set_link_bandwidth()
763 phy_cfg.dp.lanes = dp->link_train.lane_count; in analogix_dp_set_lane_count()
789 for (lane = 0; lane < dp->link_train.lane_count; lane++) { in analogix_dp_set_lane_link_training()
790 u8 training_lane = dp->link_train.training_lane[lane]; in analogix_dp_set_lane_link_training()
795 dp->link_train.training_lane[lane]); in analogix_dp_set_lane_link_training()
805 phy_cfg.dp.lanes = dp->link_train.lane_count; in analogix_dp_set_lane_link_training()
807 drm_dp_bw_code_to_link_rate(dp->link_train.link_rate) / 100; in analogix_dp_set_lane_link_training()
H A Danalogix_dp.h609 struct link_train { struct
661 struct link_train link_train; member
/rk3399_rockchip-uboot/drivers/video/rockchip/
H A Drk_edp.c43 struct link_train link_train; member
300 if (edp->link_train.revision < 0x11) in rk_edp_link_power_up()
328 values[0] = edp->link_train.link_rate; in rk_edp_link_configure()
329 values[1] = edp->link_train.lane_count; in rk_edp_link_configure()
340 for (i = 0; i < edp->link_train.lane_count; i++) in rk_edp_set_link_training()
487 edp->link_train.lane_count); in rk_edp_link_train_cr()
500 edp->link_train.lane_count); in rk_edp_link_train_cr()
504 for (i = 0; i < edp->link_train.lane_count; i++) { in rk_edp_link_train_cr()
509 if (i == edp->link_train.lane_count) { in rk_edp_link_train_cr()
527 edp_get_adjust_train(status, edp->link_train.lane_count, in rk_edp_link_train_cr()
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dedp_rk3288.h630 struct link_train { struct