194 	lane_count = dp->link_train.lane_count;  in analogix_dp_link_start()
196 	dp->link_train.lt_state = CLOCK_RECOVERY;  in analogix_dp_link_start()
197 	dp->link_train.eq_loop = 0;  in analogix_dp_link_start()
200 		dp->link_train.cr_loop[lane] = 0;  in analogix_dp_link_start()
203 	analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);  in analogix_dp_link_start()
204 	analogix_dp_set_lane_count(dp, dp->link_train.lane_count);  in analogix_dp_link_start()
208 		drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, dp->link_train.lane_count);  in analogix_dp_link_start()
212 		buf[0] = dp->link_train.link_rate;  in analogix_dp_link_start()
213 		buf[1] = dp->link_train.lane_count;  in analogix_dp_link_start()
242 		dp->link_train.training_lane[lane] =  in analogix_dp_link_start()
332 	dp->link_train.lt_state = FAILED;  in analogix_dp_reduce_link_rate()
341 	lane_count = dp->link_train.lane_count;  in analogix_dp_get_adjust_training_lane()
355 		dp->link_train.training_lane[lane] = training_lane;  in analogix_dp_get_adjust_training_lane()
381 	lane_count = dp->link_train.lane_count;  in analogix_dp_process_clock_recovery()
402 		dp->link_train.lt_state = EQUALIZER_TRAINING;  in analogix_dp_process_clock_recovery()
423 				dp->link_train.cr_loop[lane]++;  in analogix_dp_process_clock_recovery()
432 			if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP ||  in analogix_dp_process_clock_recovery()
435 					dp->link_train.cr_loop[lane],  in analogix_dp_process_clock_recovery()
447 				   dp->link_train.training_lane, lane_count);  in analogix_dp_process_clock_recovery()
462 	lane_count = dp->link_train.lane_count;  in analogix_dp_process_equalizer_training()
486 		dp->link_train.link_rate = reg;  in analogix_dp_process_equalizer_training()
488 		dp->link_train.lane_count = reg;  in analogix_dp_process_equalizer_training()
491 		       dp->link_train.link_rate, dp->link_train.lane_count);  in analogix_dp_process_equalizer_training()
493 		dp->link_train.lt_state = FINISHED;  in analogix_dp_process_equalizer_training()
499 	dp->link_train.eq_loop++;  in analogix_dp_process_equalizer_training()
501 	if (dp->link_train.eq_loop > MAX_EQ_LOOP) {  in analogix_dp_process_equalizer_training()
515 				   dp->link_train.training_lane, lane_count);  in analogix_dp_process_equalizer_training()
575 					      dp->link_rate_table[i], dp->link_train.lane_count))  in analogix_dp_select_link_rate_from_table()
579 		    analogix_dp_link_config_validate(bw_code, dp->link_train.lane_count)) {  in analogix_dp_select_link_rate_from_table()
595 		dp->link_train.link_rate = analogix_dp_select_link_rate_from_table(dp);  in analogix_dp_select_rx_bandwidth()
601 		dp->link_train.link_rate = min_t(u32, dp->link_train.link_rate,  in analogix_dp_select_rx_bandwidth()
603 	if (!dp->link_train.link_rate)  in analogix_dp_select_rx_bandwidth()
704 	dp->link_train.lane_count = min_t(u32, dp->link_train.lane_count, max_lane);  in analogix_dp_init_training()
713 	dp->link_train.ssc = !!(dpcd & DP_MAX_DOWNSPREAD_0_5);  in analogix_dp_init_training()
725 	dp->link_train.lt_state = START;  in analogix_dp_sw_link_training()
729 		switch (dp->link_train.lt_state) {  in analogix_dp_sw_link_training()
1012 					      drm_dp_bw_code_to_link_rate(dp->link_train.link_rate),  in analogix_dp_get_output_format_by_edid()
1013 					      dp->link_train.lane_count))  in analogix_dp_get_output_format_by_edid()
1154 		ret = analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);  in analogix_dp_connector_detect()
1160 		ret = analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);  in analogix_dp_connector_detect()
1202 	max_link_rate = min_t(u32, dp->video_info.max_link_rate, dp->link_train.link_rate);  in analogix_dp_mode_valid()
1203 	max_lane_count = min_t(u32, dp->video_info.max_lane_count, dp->link_train.lane_count);  in analogix_dp_mode_valid()