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/rk3399_rockchip-uboot/drivers/i2c/
H A Ds3c24x0_i2c.c40 static int WaitForXfer(struct s3c24x0_i2c *i2c) in WaitForXfer() argument
45 if (readl(&i2c->iiccon) & I2CCON_IRPND) in WaitForXfer()
46 return (readl(&i2c->iicstat) & I2CSTAT_NACK) ? in WaitForXfer()
53 static void read_write_byte(struct s3c24x0_i2c *i2c) in read_write_byte() argument
55 clrbits_le32(&i2c->iiccon, I2CCON_IRPND); in read_write_byte()
58 static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd) in i2c_ch_init() argument
76 writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon); in i2c_ch_init()
79 writel(0, &i2c->iicstat); in i2c_ch_init()
80 writel(slaveadd, &i2c->iicadd); in i2c_ch_init()
82 writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat); in i2c_ch_init()
[all …]
H A Dexynos_hs_i2c.c103 static int hsi2c_wait_for_trx(struct exynos5_hsi2c *i2c) in hsi2c_wait_for_trx() argument
108 u32 int_status = readl(&i2c->usi_int_stat); in hsi2c_wait_for_trx()
111 u32 trans_status = readl(&i2c->usi_trans_status); in hsi2c_wait_for_trx()
114 writel(int_status, &i2c->usi_int_stat); in hsi2c_wait_for_trx()
227 struct exynos5_hsi2c *i2c = i2c_bus->hsregs; in exynos5_i2c_reset() local
231 i2c_ctl = readl(&i2c->usi_ctl); in exynos5_i2c_reset()
233 writel(i2c_ctl, &i2c->usi_ctl); in exynos5_i2c_reset()
235 i2c_ctl = readl(&i2c->usi_ctl); in exynos5_i2c_reset()
237 writel(i2c_ctl, &i2c->usi_ctl); in exynos5_i2c_reset()
260 static unsigned hsi2c_poll_fifo(struct exynos5_hsi2c *i2c, bool rx_transfer) in hsi2c_poll_fifo() argument
[all …]
H A Drk_i2c.c119 static void rk_i2c_set_clk(struct rk_i2c *i2c, unsigned int scl_rate) in rk_i2c_set_clk() argument
125 i2c_rate = clk_get_rate(&i2c->clk); in rk_i2c_set_clk()
132 writel(I2C_CLKDIV_VAL(divl, divh), &i2c->regs->clkdiv); in rk_i2c_set_clk()
137 debug("set clk(I2C_CLKDIV: 0x%08x)\n", readl(&i2c->regs->clkdiv)); in rk_i2c_set_clk()
140 static int rk_i2c_adapter_clk(struct rk_i2c *i2c, unsigned int scl_rate) in rk_i2c_adapter_clk() argument
147 unsigned int i2c_rate = clk_get_rate(&i2c->clk); in rk_i2c_adapter_clk()
201 i2c->cfg = I2C_CON_SDA_CFG(1) | I2C_CON_STA_CFG(start_setup); in rk_i2c_adapter_clk()
203 &i2c->regs->clkdiv); in rk_i2c_adapter_clk()
205 debug("set clk(I2C_TIMING: 0x%08x)\n", i2c->cfg); in rk_i2c_adapter_clk()
206 debug("set clk(I2C_CLKDIV: 0x%08x)\n", readl(&i2c->regs->clkdiv)); in rk_i2c_adapter_clk()
[all …]
H A DMakefile7 obj-$(CONFIG_DM_I2C) += i2c-uclass.o
8 obj-$(CONFIG_DM_I2C_COMPAT) += i2c-uclass-compat.o
9 obj-$(CONFIG_DM_I2C_GPIO) += i2c-gpio.o
20 obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o
37 obj-$(CONFIG_SYS_I2C_SANDBOX) += sandbox_i2c.o i2c-emul-uclass.o
42 obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o
43 obj-$(CONFIG_SYS_I2C_UNIPHIER_F) += i2c-uniphier-f.o
H A Domap24xx_i2c.c59 struct i2c *regs;
119 static int wait_for_bb(struct i2c *i2c_base, int waitdelay)
149 static u16 wait_for_event(struct i2c *i2c_base, int waitdelay)
182 static void flush_fifo(struct i2c *i2c_base)
201 static int __omap24_i2c_setspeed(struct i2c *i2c_base, uint speed,
264 static void omap24_i2c_deblock(struct i2c *i2c_base)
309 static void __omap24_i2c_init(struct i2c *i2c_base, int speed, int slaveadd,
366 static int __omap24_i2c_probe(struct i2c *i2c_base, int waitdelay, uchar chip)
429 static int __omap24_i2c_read(struct i2c *i2c_base, int waitdelay, uchar chip,
570 static int __omap24_i2c_write(struct i2c *i2c_base, int waitdelay, uchar chip,
[all …]
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dtegra186-p2771-0000.dtsi14 i2c0 = "/bpmp/i2c";
15 i2c1 = "/i2c@3160000";
16 i2c2 = "/i2c@c240000";
17 i2c3 = "/i2c@3180000";
18 i2c4 = "/i2c@3190000";
19 i2c5 = "/i2c@31c0000";
20 i2c6 = "/i2c@c250000";
21 i2c7 = "/i2c@31e0000";
33 i2c@3160000 {
37 i2c@3180000 {
[all …]
H A Dtegra210-p2571.dts14 i2c0 = "/i2c@7000d000";
15 i2c1 = "/i2c@7000c000";
16 i2c2 = "/i2c@7000c400";
17 i2c3 = "/i2c@7000c500";
18 i2c4 = "/i2c@7000c700";
19 i2c5 = "/i2c@7000d100";
32 i2c@7000c000 {
37 i2c@7000c400 {
42 i2c@7000c500 {
47 i2c@7000c700 {
[all …]
H A Dexynos4.dtsi61 i2c_0: i2c@13860000 {
64 compatible = "samsung,s3c2440-i2c";
69 i2c_1: i2c@13870000 {
72 compatible = "samsung,s3c2440-i2c";
77 i2c_2: i2c@13880000 {
80 compatible = "samsung,s3c2440-i2c";
85 i2c_3: i2c@13890000 {
88 compatible = "samsung,s3c2440-i2c";
93 i2c_4: i2c@138a0000 {
96 compatible = "samsung,s3c2440-i2c";
[all …]
H A Dtegra30-tamonten.dtsi16 i2c0 = "/i2c@7000c000";
17 i2c1 = "/i2c@7000c700";
18 i2c2 = "/i2c@7000c400";
19 i2c3 = "/i2c@7000c500";
20 i2c4 = "/i2c@7000d000";
28 i2c@7000c000 {
34 i2c@7000c400 {
39 i2c@7000c500 {
45 i2c@7000c700 {
51 i2c@7000d000 {
H A Dtegra124-venice2.dts14 i2c0 = "/i2c@7000d000";
15 i2c1 = "/i2c@7000c000";
16 i2c2 = "/i2c@7000c400";
17 i2c3 = "/i2c@7000c500";
18 i2c4 = "/i2c@7000c700";
19 i2c5 = "/i2c@7000d100";
33 i2c@7000c000 {
38 i2c@7000c400 {
43 i2c@7000c500 {
48 i2c@7000c700 {
[all …]
H A Dexynos5250-arndale.dts18 i2c0 = "/i2c@12C60000";
19 i2c1 = "/i2c@12C70000";
20 i2c2 = "/i2c@12C80000";
21 i2c3 = "/i2c@12C90000";
22 i2c4 = "/i2c@12CA0000";
23 i2c5 = "/i2c@12CB0000";
24 i2c6 = "/i2c@12CC0000";
25 i2c7 = "/i2c@12CD0000";
H A Dtegra114-dalmore.dts14 i2c0 = "/i2c@7000d000";
15 i2c1 = "/i2c@7000c000";
16 i2c2 = "/i2c@7000c400";
17 i2c3 = "/i2c@7000c500";
18 i2c4 = "/i2c@7000c700";
30 i2c@7000c000 {
35 i2c@7000c400 {
40 i2c@7000c500 {
45 i2c@7000c700 {
50 i2c@7000d000 {
H A Dexynos54xx.dtsi17 i2c0 = "/i2c@12C60000";
18 i2c1 = "/i2c@12C70000";
19 i2c2 = "/i2c@12C80000";
20 i2c3 = "/i2c@12C90000";
21 i2c4 = "/i2c@12CA0000";
22 i2c5 = "/i2c@12CB0000";
23 i2c6 = "/i2c@12CC0000";
24 i2c7 = "/i2c@12CD0000";
25 i2c8 = "/i2c@12E00000";
26 i2c9 = "/i2c@12E10000";
[all …]
H A Dtegra186.dtsi61 gen1_i2c: i2c@3160000 {
62 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
70 reset-names = "i2c";
74 cam_i2c: i2c@3180000 {
75 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
83 reset-names = "i2c";
87 dp_aux_ch1_i2c: i2c@3190000 {
88 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
96 reset-names = "i2c";
100 dp_aux_ch0_i2c: i2c@31b0000 {
[all …]
H A Dzynqmp-zcu102-revA.dts147 * i2c mw 20 6 0 - setup IO to output
148 * i2c mw 20 2 ef - setup output values on pins 0-7
149 * i2c mw 20 3 ff - setup output values on pins 10-17
194 tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */
225 i2c@0 { /* i2c mw 75 0 1 */
281 i2c@1 { /* i2c mw 75 0 1 */
327 i2c@2 { /* i2c mw 75 0 1 */
404 /* FIXME PL i2c via PCA9306 - u45 */
411 i2c@0 { /* i2c mw 74 0 1 */
428 i2c@1 { /* i2c mw 74 0 2 */
[all …]
H A Dtegra20-plutux.dts26 i2c@7000c000 {
30 i2c@7000c400 {
34 i2c@7000c500 {
38 i2c@7000d000 {
H A Dexynos5250.dtsi50 i2c_4: i2c@12CA0000 {
51 compatible = "samsung,s3c2440-i2c";
58 i2c_5: i2c@12CB0000 {
59 compatible = "samsung,s3c2440-i2c";
66 i2c_6: i2c@12CC0000 {
67 compatible = "samsung,s3c2440-i2c";
74 i2c_7: i2c@12CD0000 {
75 compatible = "samsung,s3c2440-i2c";
H A Dexynos5250-snow.dts23 i2c0 = "/i2c@12C60000";
24 i2c1 = "/i2c@12C70000";
25 i2c2 = "/i2c@12C80000";
26 i2c3 = "/i2c@12C90000";
27 i2c4 = "/i2c@12CA0000";
29 i2c5 = "/i2c@12CB0000";
30 i2c6 = "/i2c@12CC0000";
31 i2c7 = "/i2c@12CD0000";
98 i2c-arbitrator {
99 compatible = "i2c-arb-gpio-challenge";
[all …]
H A Dexynos4412-odroid.dts18 i2c0 = "/i2c@13860000";
19 i2c1 = "/i2c@13870000";
20 i2c2 = "/i2c@13880000";
21 i2c3 = "/i2c@13890000";
22 i2c4 = "/i2c@138a0000";
23 i2c5 = "/i2c@138b0000";
24 i2c6 = "/i2c@138c0000";
25 i2c7 = "/i2c@138d0000";
32 i2c@13860000 {
33 samsung,i2c-sda-delay = <100>;
[all …]
H A Dtegra30-colibri.dts14 i2c0 = "/i2c@7000d000";
15 i2c1 = "/i2c@7000c000";
16 i2c2 = "/i2c@7000c700";
34 i2c@7000c000 {
44 i2c@7000c700 {
53 i2c@7000d000 {
/rk3399_rockchip-uboot/doc/device-tree-bindings/i2c/
H A Di2c-at91.txt4 - compatible : Must be "atmel,at91rm9200-i2c", "atmel,at91sam9261-i2c",
5 "atmel,at91sam9260-i2c", "atmel,at91sam9g20-i2c", "atmel,at91sam9g10-i2c",
6 "atmel,at91sam9x5-i2c", "atmel,sama5d4-i2c" or "atmel,sama5d2-i2c".
15 - Child nodes conforming to i2c bus binding.
19 i2c0: i2c@f8028000 {
20 compatible = "atmel,sama5d2-i2c";
H A Di2c-gpio.txt5 - drivers/i2c/i2c-gpio.c
7 Software i2c device-tree node properties:
11 * compatible = "i2c-gpio";
15 * i2c-gpio,delay-us = <5>;
22 i2c-gpio@1 {
26 compatible = "i2c-gpio";
30 i2c-gpio,delay-us = <5>;
H A Di2c-mux.txt1 Common i2c bus multiplexer/switch properties.
3 An i2c bus multiplexer/switch will have several child busses that are
4 numbered uniquely in a device dependent manner. The nodes for an i2c bus
19 - Child nodes conforming to i2c bus binding
36 i2c@3 {
48 i2c@4 {
/rk3399_rockchip-uboot/drivers/i2c/muxes/
H A DMakefile6 obj-$(CONFIG_I2C_ARB_GPIO_CHALLENGE) += i2c-arb-gpio-challenge.o
7 obj-$(CONFIG_$(SPL_)I2C_MUX) += i2c-mux-uclass.o
9 obj-$(CONFIG_I2C_MUX_GPIO) += i2c-mux-gpio.o
/rk3399_rockchip-uboot/include/configs/
H A Dp1_p2_rdb_pc.h847 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
848 i2c mw 18 3 __SW_BOOT_MASK 1; reset
852 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
853 i2c mw 18 3 __SW_BOOT_MASK 1; reset
857 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
858 i2c mw 18 3 __SW_BOOT_MASK 1; reset
862 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
863 i2c mw 18 3 __SW_BOOT_MASK 1; reset
867 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
868 i2c mw 18 3 __SW_BOOT_MASK 1; reset

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