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Searched refs:fsp (Results 1 – 16 of 16) sorted by relevance

/rk3399_rockchip-uboot/doc/device-tree-bindings/misc/
H A Dintel,baytrail-fsp.txt8 arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h, under the same names, and in
14 - fsp,enable-sdio
15 - fsp,enable-sdcard
16 - fsp,enable-hsuart0
17 - fsp,enable-hsuart1
18 - fsp,enable-spi
19 - fsp,enable-sata
20 - fsp,enable-azalia
21 - fsp,enable-xhci
22 - fsp,enable-dma0
[all …]
/rk3399_rockchip-uboot/arch/x86/dts/
H A Ddfi-bt700.dtsi8 #include <asm/arch-baytrail/fsp/fsp_configs.h>
259 fsp {
260 compatible = "intel,baytrail-fsp";
261 fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
262 fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
263 fsp,mrc-init-spd-addr1 = <0xa0>;
264 fsp,mrc-init-spd-addr2 = <0xa2>;
265 fsp,emmc-boot-mode = <EMMC_BOOT_MODE_AUTO>;
266 fsp,enable-sdio;
267 fsp,enable-sdcard;
[all …]
H A Dminnowmax.dts9 #include <asm/arch-baytrail/fsp/fsp_configs.h>
262 fsp {
263 compatible = "intel,baytrail-fsp";
264 fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
265 fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
266 fsp,mrc-init-spd-addr1 = <0xa0>;
267 fsp,mrc-init-spd-addr2 = <0xa2>;
268 fsp,emmc-boot-mode = <EMMC_BOOT_MODE_AUTO>;
269 fsp,enable-sdio;
270 fsp,enable-sdcard;
[all …]
H A Dconga-qeval20-qa3-e3845.dts10 #include <asm/arch-baytrail/fsp/fsp_configs.h>
248 fsp {
249 compatible = "intel,baytrail-fsp";
250 fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
251 fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
252 fsp,mrc-init-spd-addr1 = <0xa0>;
253 fsp,mrc-init-spd-addr2 = <0xa2>;
254 fsp,emmc-boot-mode = <EMMC_BOOT_MODE_AUTO>;
255 fsp,enable-sdio;
256 fsp,enable-sdcard;
[all …]
H A Dbayleybay.dts9 #include <asm/arch-baytrail/fsp/fsp_configs.h>
238 fsp {
239 compatible = "intel,baytrail-fsp";
240 fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
241 fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
242 fsp,mrc-init-spd-addr1 = <0xa0>;
243 fsp,mrc-init-spd-addr2 = <0xa2>;
244 fsp,emmc-boot-mode = <EMMC_BOOT_MODE_AUTO>;
245 fsp,enable-sdio;
246 fsp,enable-sdcard;
[all …]
H A Dbaytrail_som-db5800-som-6867.dts10 #include <asm/arch-baytrail/fsp/fsp_configs.h>
261 fsp {
262 compatible = "intel,baytrail-fsp";
263 fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
264 fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
265 fsp,mrc-init-spd-addr1 = <0xa0>;
266 fsp,mrc-init-spd-addr2 = <0xa2>;
267 fsp,enable-spi;
268 fsp,enable-sata;
269 fsp,sata-mode = <SATA_MODE_AHCI>;
[all …]
H A Dcougarcanyon2.dts49 fsp {
50 compatible = "intel,ivybridge-fsp";
51 fsp,enable-ht;
H A Du-boot.dtsi53 intel-fsp {
/rk3399_rockchip-uboot/arch/x86/lib/fsp/
H A Dfsp_support.c45 volatile register u8 *fsp asm("eax"); in find_fsp_header()
48 fsp = (u8 *)CONFIG_FSP_ADDR; in find_fsp_header()
51 if (((struct fv_header *)fsp)->sign == EFI_FVH_SIGNATURE) { in find_fsp_header()
53 fsp += ((struct fv_header *)fsp)->ext_hdr_off; in find_fsp_header()
54 fsp += ((struct fv_ext_header *)fsp)->ext_hdr_size; in find_fsp_header()
55 fsp = (u8 *)(((u32)fsp + 7) & 0xFFFFFFF8); in find_fsp_header()
57 fsp = 0; in find_fsp_header()
61 if (fsp && in find_fsp_header()
62 ((struct ffs_file_header *)fsp)->name.data1 == FSP_GUID_DATA1 && in find_fsp_header()
63 ((struct ffs_file_header *)fsp)->name.data2 == FSP_GUID_DATA2 && in find_fsp_header()
[all …]
H A Dcmd_fsp.c128 fsp, 2, 1, do_fsp,
/rk3399_rockchip-uboot/cmd/ddr_tool/ddr_dq_eye/
H A Dddr_dq_eye.c180 u8 fsp = 0; in do_ddr_dq_eye() local
208 if (result.fsp_mhz[i] > result.fsp_mhz[fsp]) in do_ddr_dq_eye()
209 fsp = i; in do_ddr_dq_eye()
217 fsp = (u8)freq_mhz; in do_ddr_dq_eye()
219 for (fsp = 0; fsp < FSP_NUM; fsp++) in do_ddr_dq_eye()
220 if (result.fsp_mhz[fsp] == freq_mhz || in do_ddr_dq_eye()
221 result.fsp_mhz[fsp] == (u16)(freq_mhz / MHZ)) in do_ddr_dq_eye()
224 if (fsp >= FSP_NUM) in do_ddr_dq_eye()
234 if (result.fsp_mhz[fsp] < in do_ddr_dq_eye()
247 if (result.fsp_mhz[fsp] < in do_ddr_dq_eye()
[all …]
/rk3399_rockchip-uboot/tools/binman/test/
H A D42_intel-fsp.dts10 intel-fsp {
11 filename = "fsp.bin";
/rk3399_rockchip-uboot/arch/x86/lib/
H A DMakefile49 obj-$(CONFIG_HAVE_FSP) += fsp/
/rk3399_rockchip-uboot/drivers/ram/rockchip/
H A Dsdram_rv1126.c2100 u32 fsp) in high_freq_training() argument
2151 ret = data_training(dram, 0, sdram_params, fsp, READ_GATE_TRAINING | in high_freq_training()
2154 rw_trn_result.fsp_mhz[fsp] = (u16)sdram_params->base.ddr_freq; in high_freq_training()
2155 save_rw_trn_min_max(phy_base, &rw_trn_result.rd_fsp[fsp].cs[0], in high_freq_training()
2156 &rw_trn_result.wr_fsp[fsp].cs[0], in high_freq_training()
2164 ret |= data_training(dram, 1, sdram_params, fsp, in high_freq_training()
2168 save_rw_trn_min_max(phy_base, &rw_trn_result.rd_fsp[fsp].cs[1], in high_freq_training()
2169 &rw_trn_result.wr_fsp[fsp].cs[1], in high_freq_training()
2183 save_rw_trn_deskew(phy_base, &rw_trn_result.rd_fsp[fsp], in high_freq_training()
2200 save_rw_trn_deskew(phy_base, &rw_trn_result.wr_fsp[fsp], in high_freq_training()
/rk3399_rockchip-uboot/doc/
H A DREADME.x86218 Rename the first one to fsp.bin and second one to cmc.bin and put them in the
244 time of writing) in the board directory and rename it to fsp.bin.
266 it to fsp.bin.
308 69f65b9a580246291d20d08cbef9d7c5 board/intel/minnowmax/fsp.bin
323 7c0000 fsp.bin CONFIG_FSP_ADDR
324 7f8000 <spare> (depends on size of fsp.bin)
532 fsp - Display information about Intel Firmware Support Package (FSP).
1139 [5] http://www.intel.com/fsp
/rk3399_rockchip-uboot/arch/x86/
H A DKconfig353 default "fsp.bin"
423 please check FSP output HOB via U-Boot command 'fsp hob' to see
424 if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp/fsp_hob.h).