1*a2e3b05eSBin Meng/* 2*a2e3b05eSBin Meng * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> 3*a2e3b05eSBin Meng * 4*a2e3b05eSBin Meng * SPDX-License-Identifier: GPL-2.0+ 5*a2e3b05eSBin Meng */ 6*a2e3b05eSBin Meng 7*a2e3b05eSBin Meng/dts-v1/; 8*a2e3b05eSBin Meng 9*a2e3b05eSBin Meng/include/ "skeleton.dtsi" 10*a2e3b05eSBin Meng/include/ "serial.dtsi" 11*a2e3b05eSBin Meng/include/ "keyboard.dtsi" 12*a2e3b05eSBin Meng/include/ "rtc.dtsi" 13*a2e3b05eSBin Meng/include/ "tsc_timer.dtsi" 14*a2e3b05eSBin Meng 15*a2e3b05eSBin Meng/ { 16*a2e3b05eSBin Meng model = "Intel Cougar Canyon 2"; 17*a2e3b05eSBin Meng compatible = "intel,cougarcanyon2", "intel,chiefriver"; 18*a2e3b05eSBin Meng 19*a2e3b05eSBin Meng aliases { 20*a2e3b05eSBin Meng spi0 = &spi0; 21*a2e3b05eSBin Meng }; 22*a2e3b05eSBin Meng 23*a2e3b05eSBin Meng config { 24*a2e3b05eSBin Meng silent_console = <0>; 25*a2e3b05eSBin Meng }; 26*a2e3b05eSBin Meng 27*a2e3b05eSBin Meng chosen { 28*a2e3b05eSBin Meng stdout-path = "/serial"; 29*a2e3b05eSBin Meng }; 30*a2e3b05eSBin Meng 31*a2e3b05eSBin Meng microcode { 32*a2e3b05eSBin Meng update@0 { 33*a2e3b05eSBin Meng#include "microcode/m12306a2_00000008.dtsi" 34*a2e3b05eSBin Meng }; 35*a2e3b05eSBin Meng update@1 { 36*a2e3b05eSBin Meng#include "microcode/m12306a4_00000007.dtsi" 37*a2e3b05eSBin Meng }; 38*a2e3b05eSBin Meng update@2 { 39*a2e3b05eSBin Meng#include "microcode/m12306a5_00000007.dtsi" 40*a2e3b05eSBin Meng }; 41*a2e3b05eSBin Meng update@3 { 42*a2e3b05eSBin Meng#include "microcode/m12306a8_00000010.dtsi" 43*a2e3b05eSBin Meng }; 44*a2e3b05eSBin Meng update@4 { 45*a2e3b05eSBin Meng#include "microcode/m12306a9_0000001b.dtsi" 46*a2e3b05eSBin Meng }; 47*a2e3b05eSBin Meng }; 48*a2e3b05eSBin Meng 49*a2e3b05eSBin Meng fsp { 50*a2e3b05eSBin Meng compatible = "intel,ivybridge-fsp"; 51*a2e3b05eSBin Meng fsp,enable-ht; 52*a2e3b05eSBin Meng }; 53*a2e3b05eSBin Meng 54*a2e3b05eSBin Meng pci { 55*a2e3b05eSBin Meng #address-cells = <3>; 56*a2e3b05eSBin Meng #size-cells = <2>; 57*a2e3b05eSBin Meng compatible = "pci-x86"; 58*a2e3b05eSBin Meng u-boot,dm-pre-reloc; 59*a2e3b05eSBin Meng ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000 60*a2e3b05eSBin Meng 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000 61*a2e3b05eSBin Meng 0x01000000 0x0 0x2000 0x2000 0 0xe000>; 62*a2e3b05eSBin Meng 63*a2e3b05eSBin Meng pch@1f,0 { 64*a2e3b05eSBin Meng reg = <0x0000f800 0 0 0 0>; 65*a2e3b05eSBin Meng compatible = "intel,bd82x6x"; 66*a2e3b05eSBin Meng u-boot,dm-pre-reloc; 67*a2e3b05eSBin Meng #address-cells = <1>; 68*a2e3b05eSBin Meng #size-cells = <1>; 69*a2e3b05eSBin Meng 70*a2e3b05eSBin Meng spi0: spi { 71*a2e3b05eSBin Meng #address-cells = <1>; 72*a2e3b05eSBin Meng #size-cells = <0>; 73*a2e3b05eSBin Meng compatible = "intel,ich9-spi"; 74*a2e3b05eSBin Meng spi-flash@0 { 75*a2e3b05eSBin Meng reg = <0>; 76*a2e3b05eSBin Meng compatible = "winbond,w25q64bv", "spi-flash"; 77*a2e3b05eSBin Meng memory-map = <0xff800000 0x00800000>; 78*a2e3b05eSBin Meng }; 79*a2e3b05eSBin Meng }; 80*a2e3b05eSBin Meng 81*a2e3b05eSBin Meng gpioa { 82*a2e3b05eSBin Meng compatible = "intel,ich6-gpio"; 83*a2e3b05eSBin Meng u-boot,dm-pre-reloc; 84*a2e3b05eSBin Meng reg = <0 0x10>; 85*a2e3b05eSBin Meng bank-name = "A"; 86*a2e3b05eSBin Meng }; 87*a2e3b05eSBin Meng 88*a2e3b05eSBin Meng gpiob { 89*a2e3b05eSBin Meng compatible = "intel,ich6-gpio"; 90*a2e3b05eSBin Meng u-boot,dm-pre-reloc; 91*a2e3b05eSBin Meng reg = <0x30 0x10>; 92*a2e3b05eSBin Meng bank-name = "B"; 93*a2e3b05eSBin Meng }; 94*a2e3b05eSBin Meng 95*a2e3b05eSBin Meng gpioc { 96*a2e3b05eSBin Meng compatible = "intel,ich6-gpio"; 97*a2e3b05eSBin Meng u-boot,dm-pre-reloc; 98*a2e3b05eSBin Meng reg = <0x40 0x10>; 99*a2e3b05eSBin Meng bank-name = "C"; 100*a2e3b05eSBin Meng }; 101*a2e3b05eSBin Meng }; 102*a2e3b05eSBin Meng }; 103*a2e3b05eSBin Meng 104*a2e3b05eSBin Meng}; 105