| /rk3399_rockchip-uboot/drivers/i2c/ |
| H A D | ihs_i2c.c | 18 #define I2C_SET_REG(fld, val) \ argument
21 FPGA_SET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
23 FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
26 #define I2C_SET_REG(fld, val) \ argument
27 FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
31 #define I2C_GET_REG(fld, val) \ argument
34 FPGA_GET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
36 FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
39 #define I2C_GET_REG(fld, val) \ argument
40 FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
|
| /rk3399_rockchip-uboot/tools/ |
| H A D | ublimage.c | 74 char *name, int lineno, int fld, int dcd_len) in parse_cfg_cmd() argument
110 char *token, char *name, int lineno, int fld, int *dcd_len) in parse_cfg_fld() argument
113 switch (fld) { in parse_cfg_fld()
124 parse_cfg_cmd(ublhdr, *cmd, token, name, lineno, fld, *dcd_len); in parse_cfg_fld()
138 int fld; in parse_cfg_file() local
168 for (fld = CFG_COMMAND, cmd = CMD_INVALID, in parse_cfg_file()
169 line = token; ; line = NULL, fld++) { in parse_cfg_file()
179 lineno, fld, &dcd_len); in parse_cfg_file()
|
| H A D | imximage.c | 145 int fld, uint32_t value, uint32_t off) in set_dcd_val_v1() argument
149 switch (fld) { in set_dcd_val_v1()
239 int fld, uint32_t value, uint32_t off) in set_dcd_val_v2() argument
247 switch (fld) { in set_dcd_val_v2()
596 char *name, int lineno, int fld, int dcd_len) in parse_cfg_cmd() argument
655 (*set_dcd_val)(imxhdr, name, lineno, fld, value, dcd_len); in parse_cfg_cmd()
678 char *token, char *name, int lineno, int fld, int *dcd_len) in parse_cfg_fld() argument
682 switch (fld) { in parse_cfg_fld()
693 parse_cfg_cmd(imxhdr, *cmd, token, name, lineno, fld, *dcd_len); in parse_cfg_fld()
707 (*set_dcd_val)(imxhdr, name, lineno, fld, value, in parse_cfg_fld()
[all …]
|
| H A D | aisimage.c | 262 int fld; in aisimage_generate() local
303 fld = CFG_COMMAND; in aisimage_generate()
315 switch (fld) { in aisimage_generate()
341 fld = CFG_VALUE; in aisimage_generate()
|
| /rk3399_rockchip-uboot/board/gdsys/common/ |
| H A D | osd.c | 39 #define OSD_SET_REG(screen, fld, val) \ argument
42 FPGA_SET_REG(screen - OSD_DH_BASE, osd1.fld, val); \
44 FPGA_SET_REG(screen, osd0.fld, val); \
47 #define OSD_SET_REG(screen, fld, val) \ argument
48 FPGA_SET_REG(screen, osd0.fld, val)
52 #define OSD_GET_REG(screen, fld, val) \ argument
55 FPGA_GET_REG(screen - OSD_DH_BASE, osd1.fld, val); \
57 FPGA_GET_REG(screen, osd0.fld, val); \
60 #define OSD_GET_REG(screen, fld, val) \ argument
61 FPGA_GET_REG(screen, osd0.fld, val)
|
| /rk3399_rockchip-uboot/include/ |
| H A D | gdsys_fpga.h | 26 #define FPGA_SET_REG(ix, fld, val) \ argument
28 &fpga_ptr[ix]->fld, \
29 offsetof(struct ihs_fpga, fld), \
32 #define FPGA_GET_REG(ix, fld, val) \ argument
34 &fpga_ptr[ix]->fld, \
35 offsetof(struct ihs_fpga, fld), \
|
| H A D | imximage.h | 187 int fld, uint32_t value,
|
| /rk3399_rockchip-uboot/drivers/net/ |
| H A D | cpsw.c | 240 #define desc_write(desc, fld, val) __raw_writel((u32)(val), &(desc)->fld) argument
241 #define desc_read(desc, fld) __raw_readl(&(desc)->fld) argument
242 #define desc_read_ptr(desc, fld) ((void *)__raw_readl(&(desc)->fld)) argument
244 #define chan_write(chan, fld, val) __raw_writel((u32)(val), (chan)->fld) argument
245 #define chan_read(chan, fld) __raw_readl((chan)->fld) argument
246 #define chan_read_ptr(chan, fld) ((void *)__raw_readl((chan)->fld)) argument
|