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/rk3399_rockchip-uboot/drivers/misc/
H A Dali512x.c83 void ali512x_set_fdc(int enabled, u16 io, u8 irq, u8 dma_channel) in ali512x_set_fdc() argument
88 ali_write(0x30, enabled?1:0); in ali512x_set_fdc()
89 if (enabled) { in ali512x_set_fdc()
105 void ali512x_set_pp(int enabled, u16 io, u8 irq, u8 dma_channel) in ali512x_set_pp() argument
110 ali_write(0x30, enabled?1:0); in ali512x_set_pp()
111 if (enabled) { in ali512x_set_pp()
126 void ali512x_set_uart(int enabled, int index, u16 io, u8 irq) in ali512x_set_uart() argument
131 ali_write(0x30, enabled?1:0); in ali512x_set_uart()
132 if (enabled) { in ali512x_set_uart()
152 void ali512x_set_uart2_irda(int enabled) in ali512x_set_uart2_irda() argument
[all …]
/rk3399_rockchip-uboot/include/
H A Dali512x.h22 void ali512x_set_fdc(int enabled, u16 io, u8 irq, u8 dma_channel);
23 void ali512x_set_pp(int enabled, u16 io, u8 irq, u8 dma_channel);
24 void ali512x_set_uart(int enabled, int index, u16 io, u8 irq);
25 void ali512x_set_rtc(int enabled, u16 io, u8 irq);
26 void ali512x_set_kbc(int enabled, u8 kbc_irq, u8 mouse_irq);
27 void ali512x_set_cio(int enabled);
36 void ali512x_set_uart2_irda(int enabled);
/rk3399_rockchip-uboot/drivers/watchdog/
H A Dbcm2835_wdt.c17 static __efi_runtime_data bool enabled = true; variable
23 if (enabled) in hw_watchdog_reset()
34 enabled = false; in hw_watchdog_disable()
/rk3399_rockchip-uboot/drivers/net/ldpaa_eth/
H A Dldpaa_wriop.c27 dpmac_info[dpmac_id].enabled = 0; in wriop_init_dpmac()
34 dpmac_info[dpmac_id].enabled = 1; in wriop_init_dpmac()
60 dpmac_info[i].enabled = 0; in wriop_disable_dpmac()
71 dpmac_info[i].enabled = 1; in wriop_enable_dpmac()
82 return dpmac_info[i].enabled; in wriop_is_enabled_dpmac()
153 if (dpmac_info[i].enabled) in wriop_get_enet_if()
/rk3399_rockchip-uboot/drivers/clk/
H A Dclk_sandbox.c15 bool enabled[SANDBOX_CLK_ID_COUNT]; member
52 priv->enabled[clk->id] = true; in sandbox_clk_enable()
64 priv->enabled[clk->id] = false; in sandbox_clk_disable()
106 return priv->enabled[id]; in sandbox_clk_query_enable()
/rk3399_rockchip-uboot/arch/arm/mach-mvebu/
H A Dmbus.c109 int win, int *enabled, u64 *base, in mvebu_mbus_read_window() argument
119 *enabled = 0; in mvebu_mbus_read_window()
123 *enabled = 1; in mvebu_mbus_read_window()
185 int enabled; in mvebu_mbus_window_conflicts() local
188 &enabled, &wbase, &wsize, in mvebu_mbus_window_conflicts()
191 if (!enabled) in mvebu_mbus_window_conflicts()
221 int enabled; in mvebu_mbus_find_window() local
224 &enabled, &wbase, &wsize, in mvebu_mbus_find_window()
227 if (!enabled) in mvebu_mbus_find_window()
419 int enabled; in mvebu_mbus_get_lowest_base() local
[all …]
/rk3399_rockchip-uboot/board/LaCie/netspace_v2/
H A Dkwbimage.cfg38 # bit18: 1=cpu lock transaction enabled
77 # bit0: 0, OpenPage enabled
95 # bit0: 0, DDR DLL enabled
97 # bit2: 1, DDR ODT control lsd enabled
99 # bit6: 1, DDR ODT control msb, enabled
101 # bit10: 0, differential DQS enabled
103 # bit12: 0, DDR output buffer enabled
110 # bit7 : 1 , D2P Latency enabled
113 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
123 # bit0: 1, Window enabled
H A Dkwbimage-is2.cfg38 # bit18: 1=cpu lock transaction enabled
77 # bit0: 0, OpenPage enabled
95 # bit0: 0, DDR DLL enabled
97 # bit2: 1, DDR ODT control lsd enabled
99 # bit6: 1, DDR ODT control msb, enabled
101 # bit10: 0, differential DQS enabled
103 # bit12: 0, DDR output buffer enabled
110 # bit7 : 1 , D2P Latency enabled
113 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
123 # bit0: 1, Window enabled
H A Dkwbimage-ns2l.cfg38 # bit18: 1=cpu lock transaction enabled
77 # bit0: 0, OpenPage enabled
95 # bit0: 0, DDR DLL enabled
97 # bit2: 1, DDR ODT control lsd enabled
99 # bit6: 1, DDR ODT control msb, enabled
101 # bit10: 0, differential DQS enabled
103 # bit12: 0, DDR output buffer enabled
110 # bit7 : 1 , D2P Latency enabled
113 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
123 # bit0: 1, Window enabled
/rk3399_rockchip-uboot/board/LaCie/net2big_v2/
H A Dkwbimage.cfg38 # bit18: 1=cpu lock transaction enabled
77 # bit0: 0, OpenPage enabled
95 # bit0: 0, DDR DLL enabled
97 # bit2: 1, DDR ODT control lsd enabled
99 # bit6: 1, DDR ODT control msb, enabled
101 # bit10: 0, differential DQS enabled
103 # bit12: 0, DDR output buffer enabled
110 # bit7 : 1 , D2P Latency enabled
113 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
123 # bit0: 1, Window enabled
/rk3399_rockchip-uboot/drivers/net/fm/
H A Dinit.c98 if ((fm_info[i].enabled) && (fm_info[i].index == 1)) in fm_standard_init()
108 if ((fm_info[i].enabled) && (fm_info[i].index == 2)) in fm_standard_init()
143 fm_info[i].enabled = 1; in fman_enet_init()
146 fm_info[i].enabled = 0; in fman_enet_init()
160 fm_info[i].enabled = 0; in fm_disable_port()
173 fm_info[i].enabled = 1; in fm_enable_port()
224 if (fm_info[i].enabled) in fm_info_get_enet_if()
255 if (info->enabled) { in ft_fixup_port()
/rk3399_rockchip-uboot/common/
H A Diotrace.c54 bool enabled; member
67 if (!(gd->flags & GD_FLG_RELOC) || !iotrace.enabled) in add_record()
152 iotrace.enabled = enable; in iotrace_set_enabled()
157 return iotrace.enabled; in iotrace_get_enabled()
/rk3399_rockchip-uboot/board/Marvell/guruplug/
H A Dkwbimage.cfg37 # bit18: 1=cpu lock transaction enabled
77 # bit0: 0, OpenPage enabled
95 # bit0: 0, DDR DLL enabled
101 # bit10: 0, differential DQS enabled
103 # bit12: 0, DDR output buffer enabled
113 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
123 # bit0: 1, Window enabled
130 DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
/rk3399_rockchip-uboot/board/Marvell/dreamplug/
H A Dkwbimage.cfg38 # bit18: 1=cpu lock transaction enabled
78 # bit0: 0, OpenPage enabled
96 # bit0: 0, DDR DLL enabled
102 # bit10: 0, differential DQS enabled
104 # bit12: 0, DDR output buffer enabled
114 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
124 # bit0: 1, Window enabled
131 DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
/rk3399_rockchip-uboot/board/Marvell/sheevaplug/
H A Dkwbimage.cfg37 # bit18: 1=cpu lock transaction enabled
77 # bit0: 0, OpenPage enabled
95 # bit0: 0, DDR DLL enabled
101 # bit10: 0, differential DQS enabled
103 # bit12: 0, DDR output buffer enabled
113 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
123 # bit0: 1, Window enabled
130 DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
/rk3399_rockchip-uboot/doc/
H A DREADME.t1040-l2switch53 0 enabled down 10 half
54 1 enabled down 10 half
55 2 enabled down 10 half
56 3 enabled up 1000 full
61 8 enabled up 2500 full
62 9 enabled up 2500 full
/rk3399_rockchip-uboot/board/Seagate/nas220/
H A Dkwbimage.cfg40 # bit18: 1=cpu lock transaction enabled
80 # bit0: 0, OpenPage enabled
99 # bit0: 0, DDR DLL enabled
105 # bit10: 0, differential DQS enabled
107 # bit12: 0, DDR output buffer enabled
117 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
123 # bit0: 1, Window enabled
/rk3399_rockchip-uboot/board/keymile/km_arm/
H A Dkwbimage.cfg58 # bit18: 1=cpu lock transaction enabled
98 # bit0: 0, OpenPage enabled
107 # bit0: 0, DDR DLL enabled
111 # bit6: 1, DDR ODT control msb, enabled
113 # bit10: 0, differential DQS enabled
115 # bit12: 0, DDR output buffer enabled
125 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
134 # bit0: 1, Window enabled
/rk3399_rockchip-uboot/board/Marvell/openrd/
H A Dkwbimage.cfg37 # bit18: 1=cpu lock transaction enabled
77 # bit0: 0, OpenPage enabled
95 # bit0: 0, DDR DLL enabled
101 # bit10: 0, differential DQS enabled
103 # bit12: 0, DDR output buffer enabled
113 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
123 # bit0: 1, Window enabled
130 DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
/rk3399_rockchip-uboot/lib/optee_clientApi/
H A DREADME33 | arm64 | dcache enabled | dcache enabled |
35 | arm | dcache disabled | dcache enabled |
54 102dfafc4a rochchip: board: map op-tee memory as dcache enabled
55 396e3049bd rochchip: board: only map op-tee share memory as dcache enabled
/rk3399_rockchip-uboot/board/Seagate/dockstar/
H A Dkwbimage.cfg40 # bit18: 1=cpu lock transaction enabled
80 # bit0: 0, OpenPage enabled
98 # bit0: 0, DDR DLL enabled
104 # bit10: 0, differential DQS enabled
106 # bit12: 0, DDR output buffer enabled
116 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
126 # bit0: 1, Window enabled
/rk3399_rockchip-uboot/board/Synology/ds109/
H A Dkwbimage.cfg41 # bit18: 1=cpu lock transaction enabled
81 # bit0: 0, OpenPage enabled
99 # bit0: 0, DDR DLL enabled
105 # bit10: 0, differential DQS enabled
107 # bit12: 0, DDR output buffer enabled
117 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
127 # bit0: 1, Window enabled
/rk3399_rockchip-uboot/board/Seagate/goflexhome/
H A Dkwbimage.cfg43 # bit18: 1=cpu lock transaction enabled
83 # bit0: 0, OpenPage enabled
101 # bit0: 0, DDR DLL enabled
107 # bit10: 0, differential DQS enabled
109 # bit12: 0, DDR output buffer enabled
119 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
129 # bit0: 1, Window enabled
/rk3399_rockchip-uboot/board/d-link/dns325/
H A Dkwbimage.cfg46 # bit18: 1, cpu lock transaction enabled
87 # bit0: 0, OPEn=OpenPage enabled
105 # bit0: 0, DRAM DLL enabled
111 # bit10: 0, differential DQS enabled
113 # bit12: 0, DRAM output buffer enabled
123 # bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
145 # bit0: 1, Window enabled
152 DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
153 # bit0: 1, Window enabled
181 # bit14: 1, M_STARTBURST_IN ODT enabled
/rk3399_rockchip-uboot/board/cloudengines/pogo_e02/
H A Dkwbimage.cfg41 # bit18: 1=cpu lock transaction enabled
81 # bit0: 0, OpenPage enabled
99 # bit0: 0, DDR DLL enabled
105 # bit10: 0, differential DQS enabled
107 # bit12: 0, DDR output buffer enabled
117 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
127 # bit0: 1, Window enabled

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