Searched refs:drate (Results 1 – 5 of 5) sorted by relevance
| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/ |
| H A D | rockchip_dmc.h | 14 int rockchip_ddrclk_sip_set_rate_v2(unsigned long drate);
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| H A D | clock.h | 146 ulong drate) in rockchip_pll_set_rate() argument
160 ulong drate);
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| /rk3399_rockchip-uboot/drivers/clk/rockchip/ |
| H A D | clk_pll.c | 293 ulong drate) in rk3036_pll_set_rate() argument
298 rate = rockchip_get_pll_settings(pll, drate); in rk3036_pll_set_rate()
446 ulong drate) in rk3588_pll_set_rate() argument
450 rate = rockchip_get_pll_settings(pll, drate); in rk3588_pll_set_rate()
648 ulong drate) in rockchip_pll_set_rate() argument
652 if (rockchip_pll_get_rate(pll, base, pll_id) == drate) in rockchip_pll_set_rate()
658 ret = rk3036_pll_set_rate(pll, base, pll_id, drate); in rockchip_pll_set_rate()
662 ret = rk3036_pll_set_rate(pll, base, pll_id, drate); in rockchip_pll_set_rate()
666 ret = rk3588_pll_set_rate(pll, base, pll_id, drate); in rockchip_pll_set_rate()
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| H A D | clk_px30.c | 107 static struct pll_rate_table *pll_clk_set_by_auto(u32 drate) in pll_clk_set_by_auto() argument
117 u32 rate_khz = drate / KHz; in pll_clk_set_by_auto()
119 if (!drate) { in pll_clk_set_by_auto()
216 unsigned long drate) in rkclk_set_pll() argument
221 rate = get_pll_settings(drate); in rkclk_set_pll()
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| /rk3399_rockchip-uboot/drivers/ram/rockchip/ |
| H A D | rockchip_dmc.c | 819 int rockchip_ddrclk_sip_set_rate_v2(unsigned long drate) in rockchip_ddrclk_sip_set_rate_v2() argument
826 p->hz = drate; in rockchip_ddrclk_sip_set_rate_v2()
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