| /rk3399_rockchip-uboot/arch/sh/lib/ |
| H A D | udivsi3.S | 16 div1 r5,r4
18 div1 r5,r4; div1 r5,r4; div1 r5,r4
19 div1 r5,r4; div1 r5,r4; div1 r5,r4; rts; div1 r5,r4
22 div1 r5,r4; rotcl r0
23 div1 r5,r4; rotcl r0
24 div1 r5,r4; rotcl r0
25 rts; div1 r5,r4
38 div1 r5,r4
44 div1 r5,r4
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| H A D | udivsi3_i4i-Os.S | 38 div1 r5,r4
40 div1 r5,r4
41 div1 r5,r4
43 div1 r5,r4
48 div1 r5,r4
50 div1 r5,r4
58 div1 r5,r4
60 div1 r5,r4; div1 r5,r4; div1 r5,r4
61 div1 r5,r4; div1 r5,r4; rts; div1 r5,r4
65 div1 r5,r4
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| H A D | udivsi3_i4i.S | 55 div1 r5,r0
57 div1 r5,r0
58 div1 r5,r0
60 div1 r5,r0
102 div1 r5,r0
109 div1 r5,r0
112 div1 r5,r0
115 div1 r5,r0
118 div1 r5,r0
120 div1 r5,r0
[all …]
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| H A D | udiv_qrnnd.S | 29 div1 r6,r0
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| /rk3399_rockchip-uboot/drivers/clk/ |
| H A D | clk_zynq.c | 228 u32 clk_ctrl, div0, div1; in zynq_clk_get_dci_rate() local
233 div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT; in zynq_clk_get_dci_rate()
236 zynq_clk_get_pll_rate(priv, ddrpll_clk), div0), div1); in zynq_clk_get_dci_rate()
245 u32 div1 = 1; in zynq_clk_get_peripheral_rate() local
255 div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT; in zynq_clk_get_peripheral_rate()
256 if (!div1) in zynq_clk_get_peripheral_rate()
257 div1 = 1; in zynq_clk_get_peripheral_rate()
267 div1); in zynq_clk_get_peripheral_rate()
290 u32 *div0, u32 *div1) in zynq_clk_calc_peripheral_two_divs() argument
304 *div1 = d1; in zynq_clk_calc_peripheral_two_divs()
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| H A D | clk_zynqmp.c | 393 u32 div1 = 1; in zynqmp_clk_get_peripheral_rate() local
408 div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT; in zynqmp_clk_get_peripheral_rate()
409 if (!div1) in zynqmp_clk_get_peripheral_rate()
410 div1 = 1; in zynqmp_clk_get_peripheral_rate()
420 DIV_ROUND_CLOSEST(pllrate, div0), div1); in zynqmp_clk_get_peripheral_rate()
425 u32 *div0, u32 *div1) in zynqmp_clk_calc_peripheral_two_divs() argument
439 *div1 = d1; in zynqmp_clk_calc_peripheral_two_divs()
454 u32 clk_ctrl, div0 = 0, div1 = 0; in zynqmp_clk_set_peripheral_rate() local
476 &div0, &div1); in zynqmp_clk_set_peripheral_rate()
477 clk_ctrl |= div1 << CLK_CTRL_DIV1_SHIFT; in zynqmp_clk_set_peripheral_rate()
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| /rk3399_rockchip-uboot/arch/arm/mach-sunxi/ |
| H A D | clock_sun8i_a83t.c | 112 unsigned int div1 = 0, div2 = 0; in clock_set_pll5() local
118 div1 << CCM_PLL5_DIV1_SHIFT, &ccm->pll5_cfg); in clock_set_pll5()
131 int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >> in clock_get_pll6() local
135 return 24000000 * n / div1 / div2; in clock_get_pll6()
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| /rk3399_rockchip-uboot/arch/arm/mach-s5pc1xx/include/mach/ |
| H A D | clock.h | 30 unsigned int div1; member
66 unsigned int div1; member
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| /rk3399_rockchip-uboot/board/samsung/smdkc100/ |
| H A D | onenand.c | 41 value = readl(&clk->div1); in onenand_board_init()
44 writel(value, &clk->div1); in onenand_board_init()
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| /rk3399_rockchip-uboot/arch/arm/mach-keystone/include/mach/ |
| H A D | clock_defs.h | 22 u32 div1; /* 18 */ member
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| /rk3399_rockchip-uboot/drivers/video/drm/rk628/ |
| H A D | rk628_cru.c | 135 u64 foutvco, foutpostdiv, div1, div2; in rk628_cru_clk_set_rate_pll() local
177 div1 = DIV_ROUND_UP(MIN_FVCO_RATE, fout); in rk628_cru_clk_set_rate_pll()
179 for (postdiv = div1; postdiv <= div2; postdiv++) { in rk628_cru_clk_set_rate_pll()
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| /rk3399_rockchip-uboot/arch/arm/mach-keystone/ |
| H A D | clock.c | 131 offset = pllctl_reg(data->pll, div1) + i; in configure_main_pll()
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