xref: /rk3399_rockchip-uboot/arch/arm/mach-s5pc1xx/include/mach/clock.h (revision a71d99ac03c8d5d9622962344485b04aade27b67)
1*225f5eecSMinkyu Kang /*
2*225f5eecSMinkyu Kang  * (C) Copyright 2009 Samsung Electronics
3*225f5eecSMinkyu Kang  * Minkyu Kang <mk7.kang@samsung.com>
4*225f5eecSMinkyu Kang  * Heungjun Kim <riverful.kim@samsung.com>
5*225f5eecSMinkyu Kang  *
6*225f5eecSMinkyu Kang  * SPDX-License-Identifier:	GPL-2.0+
7*225f5eecSMinkyu Kang  */
8*225f5eecSMinkyu Kang 
9*225f5eecSMinkyu Kang #ifndef __ASM_ARM_ARCH_CLOCK_H_
10*225f5eecSMinkyu Kang #define __ASM_ARM_ARCH_CLOCK_H_
11*225f5eecSMinkyu Kang 
12*225f5eecSMinkyu Kang #ifndef __ASSEMBLY__
13*225f5eecSMinkyu Kang struct s5pc100_clock {
14*225f5eecSMinkyu Kang 	unsigned int	apll_lock;
15*225f5eecSMinkyu Kang 	unsigned int	mpll_lock;
16*225f5eecSMinkyu Kang 	unsigned int	epll_lock;
17*225f5eecSMinkyu Kang 	unsigned int	hpll_lock;
18*225f5eecSMinkyu Kang 	unsigned char	res1[0xf0];
19*225f5eecSMinkyu Kang 	unsigned int	apll_con;
20*225f5eecSMinkyu Kang 	unsigned int	mpll_con;
21*225f5eecSMinkyu Kang 	unsigned int	epll_con;
22*225f5eecSMinkyu Kang 	unsigned int	hpll_con;
23*225f5eecSMinkyu Kang 	unsigned char	res2[0xf0];
24*225f5eecSMinkyu Kang 	unsigned int	src0;
25*225f5eecSMinkyu Kang 	unsigned int	src1;
26*225f5eecSMinkyu Kang 	unsigned int	src2;
27*225f5eecSMinkyu Kang 	unsigned int	src3;
28*225f5eecSMinkyu Kang 	unsigned char	res3[0xf0];
29*225f5eecSMinkyu Kang 	unsigned int	div0;
30*225f5eecSMinkyu Kang 	unsigned int	div1;
31*225f5eecSMinkyu Kang 	unsigned int	div2;
32*225f5eecSMinkyu Kang 	unsigned int	div3;
33*225f5eecSMinkyu Kang 	unsigned int	div4;
34*225f5eecSMinkyu Kang 	unsigned char	res4[0x1ec];
35*225f5eecSMinkyu Kang 	unsigned int	gate_d00;
36*225f5eecSMinkyu Kang 	unsigned int	gate_d01;
37*225f5eecSMinkyu Kang 	unsigned int	gate_d02;
38*225f5eecSMinkyu Kang 	unsigned char	res5[0x54];
39*225f5eecSMinkyu Kang 	unsigned int	gate_sclk0;
40*225f5eecSMinkyu Kang 	unsigned int	gate_sclk1;
41*225f5eecSMinkyu Kang };
42*225f5eecSMinkyu Kang 
43*225f5eecSMinkyu Kang struct s5pc110_clock {
44*225f5eecSMinkyu Kang 	unsigned int	apll_lock;
45*225f5eecSMinkyu Kang 	unsigned char	res1[0x4];
46*225f5eecSMinkyu Kang 	unsigned int	mpll_lock;
47*225f5eecSMinkyu Kang 	unsigned char	res2[0x4];
48*225f5eecSMinkyu Kang 	unsigned int	epll_lock;
49*225f5eecSMinkyu Kang 	unsigned char	res3[0xc];
50*225f5eecSMinkyu Kang 	unsigned int	vpll_lock;
51*225f5eecSMinkyu Kang 	unsigned char	res4[0xdc];
52*225f5eecSMinkyu Kang 	unsigned int	apll_con;
53*225f5eecSMinkyu Kang 	unsigned char	res5[0x4];
54*225f5eecSMinkyu Kang 	unsigned int	mpll_con;
55*225f5eecSMinkyu Kang 	unsigned char	res6[0x4];
56*225f5eecSMinkyu Kang 	unsigned int	epll_con;
57*225f5eecSMinkyu Kang 	unsigned char	res7[0xc];
58*225f5eecSMinkyu Kang 	unsigned int	vpll_con;
59*225f5eecSMinkyu Kang 	unsigned char	res8[0xdc];
60*225f5eecSMinkyu Kang 	unsigned int	src0;
61*225f5eecSMinkyu Kang 	unsigned int	src1;
62*225f5eecSMinkyu Kang 	unsigned int	src2;
63*225f5eecSMinkyu Kang 	unsigned int	src3;
64*225f5eecSMinkyu Kang 	unsigned char	res9[0xf0];
65*225f5eecSMinkyu Kang 	unsigned int	div0;
66*225f5eecSMinkyu Kang 	unsigned int	div1;
67*225f5eecSMinkyu Kang 	unsigned int	div2;
68*225f5eecSMinkyu Kang 	unsigned int	div3;
69*225f5eecSMinkyu Kang 	unsigned int	div4;
70*225f5eecSMinkyu Kang 	unsigned char	res10[0x1ec];
71*225f5eecSMinkyu Kang 	unsigned int	gate_d00;
72*225f5eecSMinkyu Kang 	unsigned int	gate_d01;
73*225f5eecSMinkyu Kang 	unsigned int	gate_d02;
74*225f5eecSMinkyu Kang 	unsigned char	res11[0x54];
75*225f5eecSMinkyu Kang 	unsigned int	gate_sclk0;
76*225f5eecSMinkyu Kang 	unsigned int	gate_sclk1;
77*225f5eecSMinkyu Kang };
78*225f5eecSMinkyu Kang #endif
79*225f5eecSMinkyu Kang 
80*225f5eecSMinkyu Kang #endif
81