| /rk3399_rockchip-uboot/tools/ |
| H A D | fdtgrep.c | 114 static int value_add(struct display_info *disp, struct value_node **headp, in value_add() argument
127 disp->types_inc |= type; in value_add()
129 disp->types_exc |= type; in value_add()
130 if (disp->types_inc & disp->types_exc & type) { in value_add()
230 static int display_fdt_by_regions(struct display_info *disp, const void *blob, in display_fdt_by_regions() argument
239 FILE *f = disp->fout; in display_fdt_by_regions()
245 if (disp->show_dts_version) in display_fdt_by_regions()
248 if (disp->header) { in display_fdt_by_regions()
275 if (disp->flags & FDT_REG_ADD_MEM_RSVMAP) { in display_fdt_by_regions()
316 show = in_region || disp->all; in display_fdt_by_regions()
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| /rk3399_rockchip-uboot/drivers/video/ |
| H A D | ipu_disp.c | 828 int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk, in ipu_init_sync_panel() argument
861 if (!(g_di1_tvout && (disp == 1))) { /*not round div for tvout*/ in ipu_init_sync_panel()
868 di_parent = clk_get_parent(g_di_clk[disp]); in ipu_init_sync_panel()
870 clk_round_rate(g_pixel_clk[disp], in ipu_init_sync_panel()
881 clk_set_rate(g_di_clk[disp], in ipu_init_sync_panel()
886 clk_set_parent(g_pixel_clk[disp], g_ldb_clk); in ipu_init_sync_panel()
888 if (clk_get_usecount(g_pixel_clk[disp]) != 0) in ipu_init_sync_panel()
889 clk_set_parent(g_pixel_clk[disp], g_ipu_clk); in ipu_init_sync_panel()
891 rounded_pixel_clk = clk_round_rate(g_pixel_clk[disp], pixel_clk); in ipu_init_sync_panel()
892 clk_set_rate(g_pixel_clk[disp], rounded_pixel_clk); in ipu_init_sync_panel()
[all …]
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| H A D | tegra.c | 32 struct disp_ctlr *disp; /* Display controller to use */ member
100 static int update_display_mode(struct dc_disp_reg *disp, in update_display_mode() argument
108 writel(0x0, &disp->disp_timing_opt); in update_display_mode()
110 writel(1 | 1 << 16, &disp->ref_to_sync); in update_display_mode()
111 writel(dt->hsync_len.typ | dt->vsync_len.typ << 16, &disp->sync_width); in update_display_mode()
113 &disp->back_porch); in update_display_mode()
115 &disp->front_porch); in update_display_mode()
116 writel(dt->hactive.typ | (dt->vactive.typ << 16), &disp->disp_active); in update_display_mode()
120 writel(val, &disp->data_enable_opt); in update_display_mode()
125 writel(val, &disp->disp_interface_ctrl); in update_display_mode()
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| H A D | mxc_ipuv3_fb.c | 494 static int mxcfb_probe(u32 interface_pix_fmt, uint8_t disp, in mxcfb_probe() argument
519 mxcfbi->ipu_di = disp; in mxcfb_probe()
606 uint8_t disp, in ipuv3_fb_init() argument
610 gdisp = disp; in ipuv3_fb_init()
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| H A D | ipu_regs.h | 394 #define DC_DISP_CONF2(disp) (&DC_REG->disp_conf2[disp]) argument
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| H A D | ipu.h | 229 int32_t ipu_init_sync_panel(int disp,
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| /rk3399_rockchip-uboot/drivers/video/tegra124/ |
| H A D | display.c | 61 writel(0x1, &disp_ctrl->disp.disp_timing_opt); in update_display_mode()
64 &disp_ctrl->disp.ref_to_sync); in update_display_mode()
67 &disp_ctrl->disp.sync_width); in update_display_mode()
70 timing->hback_porch.typ, &disp_ctrl->disp.back_porch); in update_display_mode()
73 timing->hfront_porch.typ, &disp_ctrl->disp.front_porch); in update_display_mode()
76 &disp_ctrl->disp.disp_active); in update_display_mode()
93 &disp_ctrl->disp.disp_clk_ctrl); in update_display_mode()
165 dc_reg_ctx[i++] = readl(&disp_ctrl->disp.ref_to_sync); in tegra_dc_sor_disable_win_short_raster()
167 &disp_ctrl->disp.ref_to_sync); in tegra_dc_sor_disable_win_short_raster()
169 dc_reg_ctx[i++] = readl(&disp_ctrl->disp.sync_width); in tegra_dc_sor_disable_win_short_raster()
[all …]
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| H A D | sor.c | 684 writel(VSYNC_H_POSITION(1), &disp_ctrl->disp.disp_timing_opt); in tegra_dc_sor_enable_dc()
790 writel(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt); in tegra_dc_sor_attach()
792 writel(0, &disp_ctrl->disp.disp_win_opt); in tegra_dc_sor_attach()
810 writel(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt); in tegra_dc_sor_attach()
964 u32 reg_val = readl(&disp_ctrl->disp.disp_win_opt); in tegra_dc_sor_enable_sor()
967 writel(reg_val, &disp_ctrl->disp.disp_win_opt); in tegra_dc_sor_enable_sor()
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| /rk3399_rockchip-uboot/drivers/video/sunxi/ |
| H A D | sunxi_de2.c | 179 struct udevice *disp, int mux, bool is_composite) in sunxi_de2_init() argument
186 disp_uc_plat = dev_get_uclass_platdata(disp); in sunxi_de2_init()
187 debug("Using device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat); in sunxi_de2_init()
188 if (display_in_use(disp)) { in sunxi_de2_init()
195 ret = device_probe(disp); in sunxi_de2_init()
202 ret = display_read_timing(disp, &timing); in sunxi_de2_init()
211 ret = display_enable(disp, 1 << l2bpp, &timing); in sunxi_de2_init()
228 struct udevice *disp; in sunxi_de2_probe() local
236 "sunxi_dw_hdmi", &disp); in sunxi_de2_probe()
244 ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, mux, in sunxi_de2_probe()
[all …]
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| /rk3399_rockchip-uboot/drivers/video/rockchip/ |
| H A D | rk_vop.c | 229 struct udevice *disp; in rk_display_init() local
250 ret = uclass_find_device_by_of_offset(UCLASS_DISPLAY, offset, &disp); in rk_display_init()
257 disp_uc_plat = dev_get_uclass_platdata(disp); in rk_display_init()
258 debug("Found device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat); in rk_display_init()
259 if (display_in_use(disp)) { in rk_display_init()
267 ret = device_probe(disp); in rk_display_init()
274 ret = display_read_timing(disp, &timing); in rk_display_init()
305 ret = display_enable(disp, 1 << l2bpp, &timing); in rk_display_init()
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| /rk3399_rockchip-uboot/drivers/bios_emulator/x86emu/ |
| H A D | ops2.c | 295 int bit,disp; in x86emuOp2_bt_R() local
310 disp = (s16)*shiftreg >> 5; in x86emuOp2_bt_R()
311 srcval = fetch_data_long(srcoffset+disp); in x86emuOp2_bt_R()
321 disp = (s16)*shiftreg >> 4; in x86emuOp2_bt_R()
322 srcval = fetch_data_word(srcoffset+disp); in x86emuOp2_bt_R()
519 int bit,disp; in x86emuOp2_bts_R() local
534 disp = (s16)*shiftreg >> 5; in x86emuOp2_bts_R()
535 srcval = fetch_data_long(srcoffset+disp); in x86emuOp2_bts_R()
538 store_data_long(srcoffset+disp, srcval | mask); in x86emuOp2_bts_R()
547 disp = (s16)*shiftreg >> 4; in x86emuOp2_bts_R()
[all …]
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| /rk3399_rockchip-uboot/arch/arm/dts/ |
| H A D | stih407-clock.dtsi | 188 "clk-tx-icn-disp-1",
194 "clk-main-disp",
195 "clk-aux-disp",
269 clock-output-names = "clk-pix-main-disp",
275 "clk-pix-aux-disp",
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| H A D | stih410-clock.dtsi | 195 "clk-tx-icn-disp-1",
201 "clk-main-disp",
202 "clk-aux-disp",
290 clock-output-names = "clk-pix-main-disp",
296 "clk-pix-aux-disp",
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| H A D | rk3288-veyron-jerry.dts | 164 avdd_1v8_disp_en: avdd-1v8-disp-en {
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| H A D | rk3288-veyron-minnie.dts | 271 avdd_1v8_disp_en: avdd-1v8-disp-en {
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| H A D | imx7ulp-evk.dts | 304 disp-dev = "mipi_dsi_northwest";
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| H A D | imx6sx.dtsi | 1120 clock-names = "disp-axi", "csi_mclk", "dcic";
1129 clock-names = "pxp-axi", "disp-axi";
1139 clock-names = "disp-axi", "csi_mclk", "dcic";
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| H A D | imx6sll.dtsi | 627 clock-names = "disp-axi", "csi_mclk", "disp_dcic";
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| H A D | imx6ull.dtsi | 989 clock-names = "disp-axi", "csi_mclk", "disp_dcic";
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| /rk3399_rockchip-uboot/include/ |
| H A D | ipu_pixfmt.h | 64 uint8_t disp,
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-tegra/ |
| H A D | dc.h | 355 struct dc_disp_reg disp; /* DISP register 0x400 ~ 0x4e4 */ member
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