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Searched refs:ddrc (Results 1 – 12 of 12) sorted by relevance

/rk3399_rockchip-uboot/board/atmel/sama5d2_ptc/
H A Dsama5d2_ptc.c208 static void ddrc_conf(struct atmel_mpddrc_config *ddrc) in ddrc_conf() argument
210 ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM); in ddrc_conf()
212 ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddrc_conf()
221 ddrc->rtr = 0x511; in ddrc_conf()
223 ddrc->tpr0 = ((6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) | in ddrc_conf()
232 ddrc->tpr1 = ((27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) | in ddrc_conf()
237 ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) | in ddrc_conf()
/rk3399_rockchip-uboot/board/atmel/sama5d2_xplained/
H A Dsama5d2_xplained.c219 static void ddrc_conf(struct atmel_mpddrc_config *ddrc) in ddrc_conf() argument
221 ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM); in ddrc_conf()
223 ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddrc_conf()
232 ddrc->rtr = 0x511; in ddrc_conf()
234 ddrc->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | in ddrc_conf()
243 ddrc->tpr1 = (27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET | in ddrc_conf()
248 ddrc->tpr2 = (0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET | in ddrc_conf()
/rk3399_rockchip-uboot/arch/arm/mach-zynq/
H A DMakefile13 obj-y += ddrc.o
/rk3399_rockchip-uboot/drivers/ddr/fsl/
H A Dctrl_regs.c2319 struct ccsr_ddr __iomem *ddrc; in compute_fsl_memctl_config_regs() local
2323 ddrc = (void *)CONFIG_SYS_FSL_DDR_ADDR; in compute_fsl_memctl_config_regs()
2327 ddrc = (void *)CONFIG_SYS_FSL_DDR2_ADDR; in compute_fsl_memctl_config_regs()
2332 ddrc = (void *)CONFIG_SYS_FSL_DDR3_ADDR; in compute_fsl_memctl_config_regs()
2337 ddrc = (void *)CONFIG_SYS_FSL_DDR4_ADDR; in compute_fsl_memctl_config_regs()
2572 ddr->debug[28] = ddr_in32(&ddrc->debug[28]); in compute_fsl_memctl_config_regs()
2580 ddr->debug[28] |= ddr_in32(&ddrc->debug[28]); in compute_fsl_memctl_config_regs()
/rk3399_rockchip-uboot/board/hisilicon/hikey/
H A DREADME123 INFO: lpddr3_freq_init, set ddrc 533mhz
126 INFO: lpddr3_freq_init, set ddrc 800mhz
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dzynq-7000.dtsi158 compatible = "xlnx,zynq-ddrc-a05";
H A Dtegra20-tamonten.dtsi183 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
H A Dtegra20-paz00.dts227 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
H A Dtegra20-ventana.dts245 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
H A Dtegra20-harmony.dts233 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
H A Dtegra20-seaboard.dts255 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
H A Dzynqmp.dtsi551 compatible = "xlnx,zynqmp-ddrc-2.40a";