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Searched refs:cr (Results 1 – 25 of 125) sorted by relevance

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/rk3399_rockchip-uboot/arch/arm/mach-imx/
H A Dddrmc-vf610.c117 writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]); in ddrmc_ctrl_init_ddr3()
118 writel(DDRMC_CR02_DRAM_TINIT(timings->tinit), &ddrmr->cr[2]); in ddrmc_ctrl_init_ddr3()
119 writel(DDRMC_CR10_TRST_PWRON(timings->trst_pwron), &ddrmr->cr[10]); in ddrmc_ctrl_init_ddr3()
121 writel(DDRMC_CR11_CKE_INACTIVE(timings->cke_inactive), &ddrmr->cr[11]); in ddrmc_ctrl_init_ddr3()
123 DDRMC_CR12_CASLAT_LIN(timings->caslat_lin), &ddrmr->cr[12]); in ddrmc_ctrl_init_ddr3()
127 &ddrmr->cr[13]); in ddrmc_ctrl_init_ddr3()
130 DDRMC_CR14_TRAS_MIN(timings->tras_min), &ddrmr->cr[14]); in ddrmc_ctrl_init_ddr3()
132 DDRMC_CR16_TRTP(timings->trtp), &ddrmr->cr[16]); in ddrmc_ctrl_init_ddr3()
134 DDRMC_CR17_TMOD(timings->tmod), &ddrmr->cr[17]); in ddrmc_ctrl_init_ddr3()
136 DDRMC_CR18_TCKE(timings->tcke), &ddrmr->cr[18]); in ddrmc_ctrl_init_ddr3()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-at91/
H A Dmpddrc.c25 static int ddr2_decodtype_is_seq(const unsigned int base, u32 cr) in ddr2_decodtype_is_seq() argument
31 (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED)) in ddr2_decodtype_is_seq()
44 u32 ba_off, cr; in ddr2_init() local
47 ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9; in ddr2_init()
48 if (ddr2_decodtype_is_seq(base, mpddr_value->cr)) in ddr2_init()
49 ba_off += ((mpddr_value->cr & ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11; in ddr2_init()
57 writel(mpddr_value->cr, &mpddr->cr); in ddr2_init()
92 cr = readl(&mpddr->cr); in ddr2_init()
93 writel(cr | ATMEL_MPDDRC_CR_DLL_RESET_ENABLED, &mpddr->cr); in ddr2_init()
106 cr = readl(&mpddr->cr); in ddr2_init()
[all …]
/rk3399_rockchip-uboot/drivers/pwm/
H A Dpwm-imx.c32 u32 cr; in pwm_config() local
40 cr = PWMCR_PRESCALER(prescale) | in pwm_config()
44 writel(cr, &pwm->cr); in pwm_config()
59 setbits_le32(&pwm->cr, PWMCR_EN); in pwm_enable()
70 clrbits_le32(&pwm->cr, PWMCR_EN); in pwm_disable()
/rk3399_rockchip-uboot/post/lib_powerpc/
H A Dcr.c50 ulong cr; member
65 ulong cr; member
88 ulong cr; member
237 ulong cr = cpu_post_cr_table1[i]; in cpu_post_test_cr() local
247 cpu_post_exec_11 (code, &res, cr); in cpu_post_test_cr()
249 ret = res == cr ? 0 : -1; in cpu_post_test_cr()
266 ASM_MCRXR(test->cr), in cpu_post_test_cr()
274 ret = xer == 0 && ((res << (4 * test->cr)) & 0xe0000000) == test->xer ? in cpu_post_test_cr()
296 cpu_post_exec_11 (code, &res, test->cr); in cpu_post_test_cr()
319 cpu_post_exec_11 (code, &res, test->cr); in cpu_post_test_cr()
H A Dsrawi.c24 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op);
100 ulong cr; in cpu_post_test_srawi() local
104 cr = 0; in cpu_post_test_srawi()
105 cpu_post_exec_21 (code, & cr, & res, test->op1); in cpu_post_test_srawi()
107 ret = res == test->res && cr == 0 ? 0 : -1; in cpu_post_test_srawi()
117 cpu_post_exec_21 (codecr, & cr, & res, test->op1); in cpu_post_test_srawi()
120 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; in cpu_post_test_srawi()
H A Dtwo.c27 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1);
120 ulong cr; in cpu_post_test_two() local
124 cr = 0; in cpu_post_test_two()
125 cpu_post_exec_21 (code, & cr, & res, test->op); in cpu_post_test_two()
127 ret = res == test->res && cr == 0 ? 0 : -1; in cpu_post_test_two()
137 cpu_post_exec_21 (codecr, & cr, & res, test->op); in cpu_post_test_two()
140 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; in cpu_post_test_two()
H A Dtwox.c27 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1);
120 ulong cr; in cpu_post_test_twox() local
124 cr = 0; in cpu_post_test_twox()
125 cpu_post_exec_21 (code, & cr, & res, test->op); in cpu_post_test_twox()
127 ret = res == test->res && cr == 0 ? 0 : -1; in cpu_post_test_twox()
137 cpu_post_exec_21 (codecr, & cr, & res, test->op); in cpu_post_test_twox()
140 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; in cpu_post_test_twox()
H A Drlwinm.c24 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1);
99 ulong cr; in cpu_post_test_rlwinm() local
103 cr = 0; in cpu_post_test_rlwinm()
104 cpu_post_exec_21 (code, & cr, & res, test->op1); in cpu_post_test_rlwinm()
106 ret = res == test->res && cr == 0 ? 0 : -1; in cpu_post_test_rlwinm()
116 cpu_post_exec_21 (codecr, & cr, & res, test->op1); in cpu_post_test_rlwinm()
119 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; in cpu_post_test_rlwinm()
H A Dcpu.c49 ulong cr = 0; in cpu_post_makecr() local
52 cr |= 0x80000000; in cpu_post_makecr()
54 cr |= 0x40000000; in cpu_post_makecr()
56 cr |= 0x20000000; in cpu_post_makecr()
58 return cr; in cpu_post_makecr()
H A Dthreex.c27 extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
173 ulong cr; in cpu_post_test_threex() local
177 cr = 0; in cpu_post_test_threex()
178 cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2); in cpu_post_test_threex()
180 ret = res == test->res && cr == 0 ? 0 : -1; in cpu_post_test_threex()
190 cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2); in cpu_post_test_threex()
193 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; in cpu_post_test_threex()
H A Drlwnm.c24 extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
109 ulong cr; in cpu_post_test_rlwnm() local
113 cr = 0; in cpu_post_test_rlwnm()
114 cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2); in cpu_post_test_rlwnm()
116 ret = res == test->res && cr == 0 ? 0 : -1; in cpu_post_test_rlwnm()
126 cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2); in cpu_post_test_rlwnm()
129 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; in cpu_post_test_rlwnm()
H A Drlwimi.c24 extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
106 ulong cr; in cpu_post_test_rlwimi() local
110 cr = 0; in cpu_post_test_rlwimi()
111 cpu_post_exec_22 (code, & cr, & res, test->op0, test->op1); in cpu_post_test_rlwimi()
113 ret = res == test->res && cr == 0 ? 0 : -1; in cpu_post_test_rlwimi()
123 cpu_post_exec_22 (codecr, & cr, & res, test->op0, test->op1); in cpu_post_test_rlwimi()
126 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; in cpu_post_test_rlwimi()
H A Dthreei.c26 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op);
97 ulong cr; in cpu_post_test_threei() local
99 cr = 0; in cpu_post_test_threei()
100 cpu_post_exec_21 (code, & cr, & res, test->op1); in cpu_post_test_threei()
102 ret = res == test->res && cr == 0 ? 0 : -1; in cpu_post_test_threei()
H A Dthree.c27 extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
203 ulong cr; in cpu_post_test_three() local
207 cr = 0; in cpu_post_test_three()
208 cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2); in cpu_post_test_three()
210 ret = res == test->res && cr == 0 ? 0 : -1; in cpu_post_test_three()
220 cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2); in cpu_post_test_three()
223 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; in cpu_post_test_three()
H A Dandi.c24 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op);
83 ulong cr; in cpu_post_test_andi() local
85 cpu_post_exec_21 (codecr, & cr, & res, test->op1); in cpu_post_test_andi()
88 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; in cpu_post_test_andi()
H A Db.c31 ulong cr);
34 int pjump, int decr, int link, ulong pctr, ulong cr) in cpu_post_test_bc() argument
56 cpu_post_exec_31 (code, &ctr, &lr, &jump, cr); in cpu_post_test_bc()
150 int cr = cond ? 0x80000000 : 0x00000000; in cpu_post_test_b() local
161 ctr, cr); in cpu_post_test_b()
/rk3399_rockchip-uboot/arch/nds32/cpu/n1213/ag101/
H A Dtimer.c22 unsigned int cr; in timer_init() local
27 writel(0, &tmr->cr); in timer_init()
46 cr = readl(&tmr->cr); in timer_init()
48 cr |= FTTMR010_TM3_CLOCK; /* use external clock */ in timer_init()
50 cr |= FTTMR010_TM3_ENABLE; in timer_init()
51 writel(cr, &tmr->cr); in timer_init()
/rk3399_rockchip-uboot/drivers/mtd/
H A Dstm32_flash.c27 setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_LOCK); in stm32_flash_lock()
102 clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SNB_MASK); in flash_erase()
105 setbits_le32(&STM32_FLASH->cr, in flash_erase()
108 setbits_le32(&STM32_FLASH->cr, in flash_erase()
114 setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SER); in flash_erase()
115 setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_STRT); in flash_erase()
120 clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SER); in flash_erase()
136 setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_PG); in write_buff()
147 clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_PG); in write_buff()
/rk3399_rockchip-uboot/drivers/timer/
H A Dag101p_timer.c59 u32 cr; /* 0x30 */ member
82 u32 cr; in atftmr_timer_probe() local
89 cr = readl(&regs->cr); in atftmr_timer_probe()
90 cr |= (T3_ENABLE|T3_UPDOWN); in atftmr_timer_probe()
91 writel(cr, &regs->cr); in atftmr_timer_probe()
/rk3399_rockchip-uboot/board/keymile/km83xx/
H A Dkm83xx_i2c.c20 out_8(&base->cr, (I2C_CR_MEN | I2C_CR_MSTA)); in i2c_write_start_seq()
22 out_8(&base->cr, (I2C_CR_MEN)); in i2c_write_start_seq()
36 out_8(&base->cr, (I2C_CR_MSTA)); in i2c_make_abort()
38 out_8(&base->cr, (I2C_CR_MEN | I2C_CR_MSTA)); in i2c_make_abort()
61 out_8(&base->cr, (I2C_CR_MEN)); in i2c_make_abort()
/rk3399_rockchip-uboot/arch/m68k/cpu/mcf547x_8x/
H A Dslicetimer.c37 out_be32(&timerp->cr, 0); in __udelay()
39 out_be32(&timerp->cr, SLT_CR_TEN); in __udelay()
46 out_be32(&timerp->cr, 0); in __udelay()
68 out_be32(&timerp->cr, 0); in timer_init()
83 out_be32(&timerp->cr, SLT_CR_RUN | SLT_CR_IEN | SLT_CR_TEN); in timer_init()
/rk3399_rockchip-uboot/drivers/spi/
H A Dzynq_spi.c42 u32 cr; /* 0x00 */ member
120 writel(confr, &regs->cr); in zynq_spi_init_hw()
146 u32 cr; in spi_cs_activate() local
156 clrbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK); in spi_cs_activate()
157 cr = readl(&regs->cr); in spi_cs_activate()
164 cr |= (~(1 << priv->cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK; in spi_cs_activate()
165 writel(cr, &regs->cr); in spi_cs_activate()
178 setbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK); in spi_cs_deactivate()
287 confr = readl(&regs->cr); in zynq_spi_set_speed()
301 writel(confr, &regs->cr); in zynq_spi_set_speed()
[all …]
/rk3399_rockchip-uboot/drivers/i2c/
H A Dfti2c010.c70 writel(CR_I2CRST, &regs->cr); in fti2c010_reset()
72 if (!(readl(&regs->cr) & CR_I2CRST)) { in fti2c010_reset()
163 writel(CR_ENABLE | CR_TBEN | CR_START, &regs->cr); in fti2c010_probe()
170 writel(CR_ENABLE | CR_TBEN, &regs->cr); in fti2c010_probe()
208 writel(CR_ENABLE | CR_TBEN | CR_START, &regs->cr); in fti2c010_read()
218 writel(ctrl, &regs->cr); in fti2c010_read()
230 writel(CR_ENABLE | CR_TBEN | CR_START, &regs->cr); in fti2c010_read()
244 writel(ctrl, &regs->cr); in fti2c010_read()
270 writel(CR_ENABLE | CR_TBEN | CR_START, &regs->cr); in fti2c010_write()
280 writel(ctrl, &regs->cr); in fti2c010_write()
[all …]
H A Dat91_i2c.c55 writel(TWI_CR_START, &reg->cr); in at91_i2c_xfer_msg()
65 writel(TWI_CR_STOP, &reg->cr); in at91_i2c_xfer_msg()
83 writel(TWI_CR_STOP, &reg->cr); in at91_i2c_xfer_msg()
101 writel(TWI_CR_LOCKCLR, &reg->cr); in at91_i2c_xfer_msg()
212 writel(TWI_CR_SWRST, &reg->cr); in at91_i2c_probe_chip()
217 writel(TWI_CR_MSEN, &reg->cr); in at91_i2c_probe_chip()
218 writel(TWI_CR_SVDIS, &reg->cr); in at91_i2c_probe_chip()
272 writel(TWI_CR_SWRST, &reg->cr); in at91_i2c_probe()
277 writel(TWI_CR_MSEN, &reg->cr); in at91_i2c_probe()
278 writel(TWI_CR_SVDIS, &reg->cr); in at91_i2c_probe()
/rk3399_rockchip-uboot/arch/arm/mach-stm32/stm32f4/
H A Dclock.c145 setbits_le32(&STM32_RCC->cr, RCC_CR_HSION); in configure_clocks()
147 clrbits_le32(&STM32_RCC->cr, (RCC_CR_HSEON | RCC_CR_CSSON in configure_clocks()
150 clrbits_le32(&STM32_RCC->cr, RCC_CR_HSEBYP); in configure_clocks()
154 setbits_le32(&STM32_RCC->cr, RCC_CR_HSEON); in configure_clocks()
155 while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY)) in configure_clocks()
160 writel(PWR_CR_VOS_SCALE_MODE_1, &STM32_PWR->cr); in configure_clocks()
174 setbits_le32(&STM32_RCC->cr, RCC_CR_PLLON); in configure_clocks()
176 while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY)) in configure_clocks()

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