42 	u32 cr;		/* 0x00 */  member
120 	writel(confr, &regs->cr);  in zynq_spi_init_hw()
146 	u32 cr;  in spi_cs_activate()  local
156 	clrbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK);  in spi_cs_activate()
157 	cr = readl(&regs->cr);  in spi_cs_activate()
164 	cr |= (~(1 << priv->cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK;  in spi_cs_activate()
165 	writel(cr, &regs->cr);  in spi_cs_activate()
178 	setbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK);  in spi_cs_deactivate()
287 	confr = readl(&regs->cr);  in zynq_spi_set_speed()
301 	writel(confr, &regs->cr);  in zynq_spi_set_speed()
317 	confr = readl(&regs->cr);  in zynq_spi_set_mode()
325 	writel(confr, &regs->cr);  in zynq_spi_set_mode()