| /rk3399_rockchip-uboot/drivers/net/fsl-mc/dpio/ |
| H A D | qbman_portal.c | 201 uint32_t *cl = qb_cl(d); in qbman_eq_desc_set_no_orp() local
203 qb_attr_code_encode(&code_eq_orp_en, cl, 0); in qbman_eq_desc_set_no_orp()
204 qb_attr_code_encode(&code_eq_cmd, cl, in qbman_eq_desc_set_no_orp()
213 uint32_t *cl = qb_cl(d); in qbman_eq_desc_set_response() local
215 qb_attr_code_encode_64(&code_eq_rsp_lo, (uint64_t *)cl, storage_phys); in qbman_eq_desc_set_response()
216 qb_attr_code_encode(&code_eq_rsp_stash, cl, !!stash); in qbman_eq_desc_set_response()
223 uint32_t *cl = qb_cl(d); in qbman_eq_desc_set_qd() local
225 qb_attr_code_encode(&code_eq_qd_en, cl, 1); in qbman_eq_desc_set_qd()
226 qb_attr_code_encode(&code_eq_tgt_id, cl, qdid); in qbman_eq_desc_set_qd()
227 qb_attr_code_encode(&code_eq_qd_bin, cl, qd_bin); in qbman_eq_desc_set_qd()
[all …]
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| /rk3399_rockchip-uboot/board/compulab/cl-som-am57x/ |
| H A D | MAINTAINERS | 4 F: board/compulab/cl-som-am57x/
5 F: include/configs/cl-som-am57x.h
6 F: configs/cl-som-am57x_defconfig
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| H A D | Kconfig | 4 default "cl-som-am57x"
10 default "cl-som-am57x"
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| H A D | Makefile | 14 obj-y += cl-som-am57x.o mux.o
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| /rk3399_rockchip-uboot/drivers/ddr/marvell/axp/ |
| H A D | ddr3_spd.c | 582 u32 cs, cl, cs_num, cs_ena; local
701 cl = ddr3_get_max_val(ddr3_div(sum_info.min_cas_lat_time,
705 cl = ddr3_div(sum_info.min_cas_lat_time, ddr_clk_time, 0);
707 if (cl < 5)
708 cl = 5;
710 DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - Cas Latency = ", cl, 1);
771 if (cl != 3)
847 if (cl < 7)
1039 reg |= (cl << (REG_READ_DATA_SAMPLE_DELAYS_OFFS * cs));
1050 reg |= ((cl + 2) <<
[all …]
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| H A D | ddr3_hw_training.h | 268 u32 cl; member
324 u32 ddr3_cl_to_valid_cl(u32 cl);
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| H A D | ddr3_dfs.c | 988 tmp = ddr3_cl_to_valid_cl(dram_info->cl); in ddr3_dfs_low_2_high()
1172 tmp = ddr3_cl_to_valid_cl(dram_info->cl); in ddr3_dfs_low_2_high()
1479 tmp = ddr3_cl_to_valid_cl(dram_info->cl) & 0xF; in ddr3_dfs_low_2_high()
1511 reg |= (dram_info->cl << in ddr3_dfs_low_2_high()
1519 reg |= ((dram_info->cl + 1) << in ddr3_dfs_low_2_high()
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| H A D | ddr3_read_leveling.c | 223 reg |= (dram_info->cl << in ddr3_read_leveling_sw()
233 reg |= ((dram_info->cl + 1) << in ddr3_read_leveling_sw()
237 reg |= ((dram_info->cl + 2) << in ddr3_read_leveling_sw()
415 rd_sample_delay = dram_info->cl; in ddr3_read_leveling_single_cs_rl_mode()
767 rd_sample_delay = dram_info->cl; in ddr3_read_leveling_single_cs_window_mode()
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| H A D | ddr3_init.h | 109 u32 ddr3_cl_to_valid_cl(u32 cl);
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| H A D | ddr3_init.c | 981 u32 ddr3_cl_to_valid_cl(u32 cl) in ddr3_cl_to_valid_cl() argument
983 switch (cl) { in ddr3_cl_to_valid_cl()
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| H A D | ddr3_hw_training.c | 136 dram_info.cl = ddr3_valid_cl_to_cl(reg); in ddr3_hw_training()
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| /rk3399_rockchip-uboot/lib/ |
| H A D | string.c | 475 unsigned long cl = 0; in memset() local
481 cl <<= 8; in memset()
482 cl |= c & 0xff; in memset()
485 *sl++ = cl; in memset()
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| /rk3399_rockchip-uboot/arch/x86/cpu/quark/ |
| H A D | dram.c | 104 mrc_params->params.cl = fdtdec_get_int(blob, node, "dram-cl", 0); in mrc_configure_params()
117 mrc_params->params.density, mrc_params->params.cl, in mrc_configure_params()
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| H A D | smc.c | 89 tcl = mrc_params->params.cl; /* CAS latency in clocks */ in prog_ddr_timing_control()
272 cas = mrc_params->params.cl; in ddrphy_init()
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| /rk3399_rockchip-uboot/drivers/bios_emulator/include/ |
| H A D | biosemu.h | 215 u8 ch, cl; member
227 u8 cl; member
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| /rk3399_rockchip-uboot/arch/arm/mach-rockchip/ |
| H A D | spl.c | 146 unsigned long cl = 0; in memset() local
152 cl <<= 8; in memset()
153 cl |= c & 0xff; in memset()
156 *sl++ = cl; in memset()
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| /rk3399_rockchip-uboot/arch/x86/include/asm/arch-quark/ |
| H A D | mrc.h | 63 uint8_t cl; member
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| /rk3399_rockchip-uboot/arch/x86/dts/ |
| H A D | galileo.dts | 64 dram-cl = <6>;
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| /rk3399_rockchip-uboot/arch/arm/mach-omap2/omap5/ |
| H A D | Kconfig | 152 source "board/compulab/cl-som-am57x/Kconfig"
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| /rk3399_rockchip-uboot/drivers/ram/rockchip/ |
| H A D | sdram_rv1126.c | 1835 u32 mr_tmp, cl, cwl, phy_fsp, offset = 0; in data_training_wr() local
1840 cl = readl(PHY_REG(phy_base, offset)); in data_training_wr()
1928 clrsetbits_le32(PHY_REG(phy_base, offset), 0x1f, cl); in data_training_wr()
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