Lines Matching refs:cl
582 u32 cs, cl, cs_num, cs_ena; local
701 cl = ddr3_get_max_val(ddr3_div(sum_info.min_cas_lat_time,
705 cl = ddr3_div(sum_info.min_cas_lat_time, ddr_clk_time, 0);
707 if (cl < 5)
708 cl = 5;
710 DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - Cas Latency = ", cl, 1);
771 if (cl != 3)
847 if (cl < 7)
1039 reg |= (cl << (REG_READ_DATA_SAMPLE_DELAYS_OFFS * cs));
1050 reg |= ((cl + 2) <<
1060 tmp = ddr3_cl_to_valid_cl(cl);
1132 reg |= (((cl - cwl + 1) & 0xF) << 4);
1133 reg |= (((cl - cwl + 6) & 0xF) << 8);
1134 reg |= ((((cl - cwl + 6) >> 4) & 0x1) << 21);
1135 reg |= (((cl - 1) & 0xF) << 12);
1136 reg |= (((cl + 6) & 0x1F) << 16);